DeHon, Andre

Book Chapter from CaltechAUTHORS

Gojman, Benjamin and Nalmela, Sirisha, el al. (2013) GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction; ISBN 978-1-4503-1887-7; Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays; 81-90; 10.1145/2435264.2435281
Mehta, Nikil and Rubin, Raphael, el al. (2012) Limit study of energy & delay benefits of component-specific routing; ISBN 978-1-4503-1155-7; Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays; 97-106; 10.1145/2145694.2145710
Kapre, Nachiket and DeHon, André (2009) Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors; ISBN 978-1-4244-3891-4; FPL: 2009 International Conference on Field Programmable Logic and Applications; 65-72; 10.1109/FPL.2009.5272548
Kapre, Nachiket and DeHon, André (2009) Accelerating SPICE Model-Evaluation using FPGAs; ISBN 978-0-7695-3716-0; Field Programmable Custom Computing Machines, 2009; 37-44; 10.1109/FCCM.2009.14
Naeimi, Helia and DeHon, André (2007) Fault Secure Encoder and Decoder for Memory Applications; ISBN 978-0-7695-2885-4; 2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems; 409-417; 10.1109/DFT.2007.54
Kapre, Nachiket and DeHon, André (2007) Optimistic Parallelization of Floating-Point Accumulation; ISBN 978-0-7695-2854-0; 18th IEEE Symposium on Computer Arithmetic; 205-216; 10.1109/ARITH.2007.25
Nomura, Kumiko and DeHon, André, el al. (2006) Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices; ISBN 978-1-4244-0390-5; 2006 1st International Conference on Nano-Networks and Workshops; 72-76; 10.1109/NANONET.2006.346226
Wrighton, Michael G. and DeHon, André M. (2006) SAT-based optimal hypergraph partitioning with replication; ISBN 0-7803-9451-8; Asia and South Pacific Conference on Design Automation, 2006; 789-795; 10.1109/ASPDAC.2006.1594782
deLorimier, Michael and Kapre, Nachiket, el al. (2006) GraphStep: A System Architecture for Sparse-Graph Algorithms; ISBN 0-7695-2661-6; FCCM 2006: 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 143-151; 10.1109/FCCM.2006.45
Kapre, Nachiket and Mehta, Nikil, el al. (2006) Packet Switched vs. Time Multiplexed FPGA Overlay Networks; ISBN 0-7695-2661-6; FCCM 2006: 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 205-216; 10.1109/FCCM.2006.55
Gojman, Benjamin and Rubin, Raphael, el al. (2006) 3D Nanowire-Based Programmable Logic; ISBN 978-1-4244-0390-5; 2006 1st International Conference on Nano-Networks and Workshops; 54-58; 10.1109/NANONET.2006.346223
Papadantonakis, Karl and Kapre, Nachiket, el al. (2005) Pipelining saturated accumulation; ISBN 0-7803-9407-0; 2005 IEEE International Conference on Field-Programmable Technology; 19-26; 10.1109/FPT.2005.1568519
DeHon, André and Likharev, Konstantin K. (2005) Hybrid CMOS/Nanoelectronic Digital Circuits: Devices, Architectures, and Design Automation; ISBN 0-7803-9254-X; ICCAD-2005 : International Conference on Computer Aided Design; 375-382; 10.1109/ICCAD.2005.1560097
deLorimier, Michael and DeHon, André (2005) Floating-Point Sparse Matrix-Vector Multiply for FPGAs; ISBN 1-59593-029-9; FPGA '05 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays; 75-85; 10.1145/1046192.1046203
DeHon, André (2005) Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays; ISBN 1-59593-029-9; Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05); 127-137; 10.1145/1046192.1046210
Naeimi, Helia and DeHon, André (2004) A greedy algorithm for tolerating defective crosspoints in nanoPLA design; ISBN 0-7803-8651-5; 2004 IEEE International Conference on Field-Programmable Technology; 49-56; 10.1109/FPT.2004.1393250
DeHon, André and Adams, Joshua, el al. (2004) Design patterns for reconfigurable computing; ISBN 0-7695-2230-0; 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 13-23; 10.1109/FCCM.2004.29
DeHon, André and Hutchings, Brad, el al. (2004) What is the Right Model for Programming and Using Modern FPGAs?; ISBN 1-58113-829-6; FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays; 119; 10.1145/968280.968281
DeHon, André and Wilson, Michael J. (2004) Nanowire-Based Sublithographic Programmable Logic Arrays; ISBN 1-58113-829-6; FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays; 123-132; 10.1145/968280.968299
Wrighton, Michael G. and DeHon, André M. (2003) Hardware-assisted simulated annealing with application for fast FPGA placement; ISBN 1-58113-651-X; FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; 33-42; 10.1145/611817.611824
Huang, Randy and Wawrzynek, John, el al. (2003) Stochastic, spatial routing for hypergraphs, trees, and meshes; ISBN 1-58113-651-X; FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; 78-87; 10.1145/611817.611830
Rubin, Raphael and DeHon, André (2003) Design of FPGA interconnect for multilevel metalization; ISBN 1-58113-651-X; FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; 154-163; 10.1145/611817.611841
Butts, Michael and DeHon, André, el al. (2002) Molecular electronics: devices, systems and tools for gigagate, gigabit chips; ISBN 0-7803-7607-2; IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002; 443-440; 10.1109/ICCAD.2002.1167569
DeHon, André (2002) Very Large Scale Spatial Computing; ISBN 978-3-540-44311-7; Unconventional Models of Computation; 27-37; 10.1007/3-540-45833-6_3
Markovskiy, Yury and Caspi, Eylon, el al. (2002) Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine; ISBN 1-58113-452-5; FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays; 196-205; 10.1145/503048.503077