<h1>Whitney, Telle</h1>
<h2>Combined from <a href="https://authors.library.caltech.edu">CaltechAUTHORS</a></h2>
<ul>
<li>Whitney, Telle and Mead, Carver (1986) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20150112-140550704">An Integer Based Hierarchical Representation for VLSI</a>; ISBN 9780262121132; Advanced research in VLSI : proceedings of the fourth MIT conference, April 7-9, 1986; 241-257</li>
<li>Whitney, Telle and Mead, Carver (1983) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20150310-155318797">Pooh: A Uniform Representation For Circuit Level Designs</a>; ISBN 0444867511; VLSI '83 : VLSI design of digital systems : proceedings of the IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration, Trondheim, Norway, 16-19 August 1983; 401-411</li>
<li>Whitney, Telle and Hedges, Tom (1982) <a href="https://resolver.caltech.edu/CaltechCSTR:1982.5029-tr-82">Pooh User's Manual</a>; <a href="https://doi.org/10.7907/hd624-pmr46">10.7907/hd624-pmr46</a></li>
<li>Whitney, Telle (1981) <a href="https://resolver.caltech.edu/CaltechCSTR:1981.4320-tr-81">A Hierarchical Design Rule Checker</a>; <a href="https://doi.org/10.7907/8jz33-x1385">10.7907/8jz33-x1385</a></li>
<li>McGrath, Edward J. and Whitney, Telle (1980) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20170802-153857139">Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking</a>; ISBN 0-89791-020-6; 17th Conference on Design Automation; 263-268; <a href="https://doi.org/10.1109/DAC.1980.1585254">10.1109/DAC.1980.1585254</a></li>
</ul>