CaltechTHESIS advisor: Monograph
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A Caltech Library Repository Feedhttp://www.rssboard.org/rss-specificationpython-feedgenenMon, 14 Oct 2024 13:27:57 -0700Electron Current Through Thin Mica Films
https://resolver.caltech.edu/CaltechETD:etd-10142002-162916
Year: 1964
DOI: 10.7907/7ENX-8503
NOTE: Text or symbols not renderable in plain ASCII are indicated by [...]. Abstract is included in .pdf document.
Muscovite mica, cleaving every 10[Angstroms], provides a crystalline insulator with uniformly parallel surfaces of well known separation ideally suited to the study of electron transport phenomena. Using a micro-splitting technique similar to that developed by Foote and Kazan, muscovite was cleaved in a vacuum of 10(^6) Torr and metal electrodes evaporated, aluminum on one side, gold on the other. The current through 30 and 40[Angstrom] films was measured as a function of voltage and temperature and analyzed in terms of the tunneling theory of Stratton. Using the actual image-force barrier shape, the approximately symmetrical volt-ampere data gave barrier heights of [?] = 0.95 and 0.93eV for the 40 and 30[Angstrom] films, respectively, for an effective mass ratio of m*/m =0.92. The theoretical temperature dependence was observed in the 40[Angstrom] film from room temperature down to liquid nitrogen temperature (77[degrees]K). Thicker films 50 to 10,000 [Angstroms], exhibited temperature dependent volt-ampere curves linear in log I versus [square root of]V over a factor of 10:1 in voltage and a thermal activation energy of 0.55eV, lower than [t]he barrier height above possibly because of injection into polaron states. Preliminary photoelectric response data yielded [?] = 0.8eV, raising some question as to the real meaning of the [?] found from tunneling theory.https://resolver.caltech.edu/CaltechETD:etd-10142002-162916l. Electronic Processes in α-Sulfur. II. Polaron Motion in a D.C. Electric Field
https://resolver.caltech.edu/CaltechTHESIS:10262015-112021684
Year: 1966
DOI: 10.7907/RK39-A748
<p>Part I: The mobilities of photo-generated electrons and holes in orthorhombic sulfur are determined by drift mobility techniques. At room temperature electron mobilities between 0.4 cm<sup>2</sup>/V-sec and 4.8 cm<sup>2</sup>/V-sec and hole mobilities of about 5.0 cm<sup>2</sup>/V-sec are reported. The temperature dependence of the electron mobility is attributed to a level of traps whose effective depth is about 0.12 eV. This value is further supported by both the voltage dependence of the space-charge-limited, D.C. photocurrents and the photocurrent versus photon energy measurements.</p>
<p>As the field is increased from 10 kV/cm to 30 kV/cm a second mechanism for electron transport becomes appreciable and eventually dominates. Evidence that this is due to impurity band conduction at an appreciably lower mobility (4.10<sup>-4</sup> cm<sup>2</sup>/V-sec) is presented. No low mobility hole current could be detected. When fields exceeding 30 kV/cm for electron transport and 35 kV/cm for hole transport are applied, avalanche phenomena are observed. The results obtained are consistent with recent energy gap studies in sulfur. </p>
<p>The theory of the transport of photo-generated carriers is modified to include the case of appreciable thermos-regeneration from the traps in one transit time.</p>
<p>Part II: An explicit formula for the electric field E necessary to accelerate an electron to a steady-state velocity v in a polarizable crystal at arbitrary temperature is determined via two methods utilizing Feynman Path Integrals. No approximation is made regarding the magnitude of the velocity or the strength of the field. However, the actual electron-lattice Coulombic interaction is approximated by a distribution of harmonic oscillator potentials. One may be able to find the “best possible” distribution of oscillators using a variational principle, but we have not been able to find the expected criterion. However, our result is relatively insensitive to the actual distribution of oscillators used, and our E-v relationship exhibits the physical behavior expected for the polaron. Threshold fields for ejecting the electron for the polaron state are calculated for several substances using numerical results for a simple oscillator distribution. </p>
https://resolver.caltech.edu/CaltechTHESIS:10262015-112021684Electron Tunneling through Thin Films of Aluminum Nitride
https://resolver.caltech.edu/CaltechETD:etd-09272002-150142
Year: 1966
DOI: 10.7907/QDH7-C768
Thin film structures involving Aluminum as the base electrode, Aluminum Nitride as the insulating layer, Magnesium, Aluminum or Gold as the counterelectrodes were fabricated by nitriding a freshly deposited Aluminum film in a Nitrogen glow discharge with the thickness of the insulator varying from some thirty to ninety Angstroms with the express purpose of studying currents arising from the tunneling of electrons through the forbidden band of the insulator. Currents understood on the basis of the presently existing tunneling theory were observed for structures having thinner insulating regions. For structures having thicker insulating regions a temperature independent excess current was observed which could not be accounted for by the present tunneling theory.
The usual analysis of tunneling assumes the energy momentum relation of the insulator forbidden band to be parabolic and the shape of the barrier separating the two metal electrodes to be trapezoidal. Any deviation from the current voltage characteristic predicted by this model is normally attributed to the lack of validity in the assumption concerning the barrier shape. Data obtained in this research indicated that the barriers of the structures investigated were trapezoidal but that the insulator energy momentum relationship was non-parabolic. Consequently, the analysis was extended to cover the case of a trapezoidal barrier with a semi-arbitrary energy momentum relationship. Greater freedom was obtained for the current voltage characteristics but certain relations between these characteristics and the insulator thickness were retained which could be used to determine whether or not the barrier of a particular structure was trapezoidal. These same relations also suggested a means of experimentally determining the insulator energy momentum relationship if the barrier could be considered trapezoidal.
The analysis was applied to the experimental data and a complete self consistent model for electron tunneling through thin insulating layers of Aluminum Nitride was obtained.https://resolver.caltech.edu/CaltechETD:etd-09272002-150142Conduction Through Thin Titanium Dioxide Films
https://resolver.caltech.edu/CaltechTHESIS:07222014-092322045
Year: 1966
DOI: 10.7907/MNGD-M461
<p>Conduction through TiO<sub>2</sub> films of thickness 100 to 450 Å
have been investigated. The samples were prepared by either
anodization of Ti evaporation of TiO<sub>2</sub>, with Au or Al evaporated
for contacts. The anodized samples exhibited considerable hysteresis due to electrical forming, however it was
possible to avoid this problem with the evaporated samples
from which complete sets of experimental results were obtained
and used in the analysis. Electrical measurements
included: the dependence of current and capacitance on dc
voltage and temperature; the dependence of capacitance and
conductance on frequency and temperature; and transient
measurements of current and capacitance. A thick (3000 Å)
evaporated TiO<sub>2</sub> film was used for measuring the dielectric
constant (27.5) and the optical dispersion, the latter being
similar to that for rutile. An electron transmission diffraction
pattern of a evaporated film indicated an essentially
amorphous structure with a short range order that could be
related to rutile. Photoresponse measurements indicated the
same band gap of about 3 ev for anodized and evaporated
films and reduced rutile crystals and gave the barrier energies
at the contacts.</p>
<p>The results are interpreted in a self consistent manner
by considering the effect of a large impurity concentration in
the films and a correspondingly large ionic space charge.
The resulting potential profile in the oxide film leads to a
thermally assisted tunneling process between the contacts and
the interior of the oxide. A general relation is derived for
the steady state current through structures of this kind. This
in turn is expressed quantitatively for each of two possible
limiting types of impurity distributions, where one type gives
barriers of an exponential shape and leads to quantitative predictions
in c lose agreement with the experimental results.
For films somewhat greater than 100 Å, the theory is formulated
essentially in terms of only the independently measured
barrier energies and a characteristic parameter of the oxide
that depends primarily on the maximum impurity concentration
at the contacts. A single value of this parameter gives consistent
agreement with the experimentally observed dependence
of both current and capacitance on dc voltage and temperature,
with the maximum impurity concentration found to be approximately
the saturation concentration quoted for rutile. This explains
the relative insensitivity of the electrical properties of
the films on the exact conditions of formation.</p>https://resolver.caltech.edu/CaltechTHESIS:07222014-092322045The Evaluation of E-k Curves from Tunneling Currents
https://resolver.caltech.edu/CaltechETD:etd-12122006-092025
Year: 1969
DOI: 10.7907/D3BX-RQ47
The basis for interpreting I-V data taken on metal-insulator-metal structures with insulator thicknesses of less than 100 Å is examined carefully. A set of experimental tests for determining the applicability of the equation linking the I-V data to the E-k curve is presented. These tests are found to be a stringent requirement on the experimental data and to support strongly the interpretation of the experimental I-V in terms of the E-k curve for the insulator. A numerical technique for obtaining the E-k curve from I-V data is presented, and applied to data taken on Al-AlN-(Mg,Au) structures where it allows the evaluation of the E-k curve for AlN throughout the forbidden gap.https://resolver.caltech.edu/CaltechETD:etd-12122006-092025Optical and Electrical Properties of α-Monoclinic Selenium
https://resolver.caltech.edu/CaltechETD:etd-09112002-170638
Year: 1969
DOI: 10.7907/WWWK-4431
NOTE: Text or symbols not renderable in plain ASCII are indicated by [...]. Abstract is included in .pdf document.
The optical absorption of [alpha]-monoclinic selenium has been measured over the range in wavelength 1.15 [micron] to 0.2775 [micron]. The data show a well defined absorption edge at 2.25 eV with further structure appearing as changes in [...] at 2.85 eV and 3.75 eV. For comparison the absorption of selenium in solutions in which it is believed to exist in the same eight-membered puckered ring as in the crystal was measured. This absorption is qualitatively different from that of the crystal.
The existence of surface barriers on [alpha]-monoclinic selenium crystals has been demonstrated. Photometric measurements indicate electron barrier heights of 1.05 eV and 1.3 eV, respectively, for Ga and Au contacts. The mobilities of holes and electrons have been measured by a time-of-flight technique to be about 0.2 [centimeters squared]/V-sec and 1.6 [centimeters squared]/V-sec, respectively, at room temperature. The hole mobility was found to be limited by traps 0.23 [plus/minus] .01 eV above the valence levels, while the electron mobility is an intrinsic mobility limited only by scattering. It was found that in the region of low carrier density (i.e. no space charge effects) the number of carriers which crossed the sample was determined by the interplay of the applied field (carrying carriers across the sample) and diffusion (carrying carriers into the metal contact where they relax). The dielectric constant, K, was determined to be 9.2 [plus/minus] .6 over the range 100 [kilohertz] to 100 [megahertz].https://resolver.caltech.edu/CaltechETD:etd-09112002-170638Properties of α-Monoclinic Selenium
https://resolver.caltech.edu/CaltechTHESIS:10072014-094710539
Year: 1970
DOI: 10.7907/2T9A-6F21
<p>The growth of bulky and platelet shaped α-monoclinic crystals is discussed. A simple method is devised for identifying and orienting them.</p>
<p>The density, previously in disagreement with the value calculated from x-ray studies, is carefully redetermined, and found to be in good agreement with the latter.</p>
<p>The relative dielectric constant is determined, an effort being made to eliminate errors inherent in previous measurements, which have not been in agreement. A two parameter model is derived which explains the anisotropy in the relative dielectric constant of orthorhombic sulfur, which is also composed of 8-atom puckered ring molecules. The model works less well for α-monoclinic selenium. The relative dielectric constant anisotropy is quite noticeable, being 6.06 along the crystal b axis, and 8.52-8.93 normal to the axis.</p>
<p>Thin crystal platelets of α-monoclinic selenium (less than 1µ thick) are used to extend optical transmission measurements up to 4.5eV. Previously the measurements extended up to 2.1 eV, limited by the thickness of the available crystals. The absorption edge is at 2.20 eV, with changes in slope of the absorption coefficient occurring at 2.85 eV and 3.8 eV. Measurement of transmission through solutions of selenium in CS_2 and trichlorethylene yield an absorption edge of 2.75 eV. There is evidence the selenium exists in solution partly as Se_8 rings, the building block of monoclinic selenium. Transmission is measured at low temperatures (80°K and 10°K) using the platelets. The absorption edge is at 2.38 eV and 2.39 eV, respectively, for the two temperatures. Measurements at low temperatures with polarized and unpolarized light reveal interesting absorption anisotropy near 2.65 eV.</p>
https://resolver.caltech.edu/CaltechTHESIS:10072014-094710539Tunneling in Schottky Barriers
https://resolver.caltech.edu/CaltechETD:etd-06212004-113629
Year: 1970
DOI: 10.7907/QC24-Z481
The tunneling characteristics of metal contacts on n-type CdTe and p-type InAs have been measured. Both the forward and reverse bias characteristics on CdTe are in good agreement with the two-band model for the energy vs. complex momentum relationship. The presence of trapping states increased the magnitude of the tunneling current at low voltage levels by providing a two-step transition. The slope of the forward bias log J vs. V curves for tunneling through the intermediate states was reduced by a factor of 2. The approximate density and energy of the trapping states was calculated from the observed J-V characteristics. The E-k dispersion relation for InAs was also determined and found to be in excellent agreement with the two-band model.
https://resolver.caltech.edu/CaltechETD:etd-06212004-113629Current Flow in Thin Solid Films: Thermionic Emission and Tunneling
https://resolver.caltech.edu/CaltechTHESIS:06112018-102411958
Year: 1971
DOI: 10.7907/Y9SR-D889
<p> Current flow in metal-GaSe-metal sandwiches is investigated. These structures are particularly well suited to the study of current flow mechanisms because sandwiches containing uniform, single crystal films of gallium selenide can be easily fabricated. The well-defined nature of these structures allows sufficient a priori knowledge of their properties to make quantitative calculation of the predictions of appropriate models of current flow meaningful. </p>
<p> As discussed in Part I, for gallium selenide films between 200 Å and 1000 Å thick, experimentally observed currents are in excellent agreement with a simple model of thermionic contact-limited current flow. This investigation presents the first unequivocal evidence for contact-limited thermionic currents in solids.</p>
<p>In Part II films less than 100 Å thick are studied. For this thickness range, direct, inter-electrode tunneling is shown to be the dominant mechanism of current flow and an accurate energy-momentum dispersion relation within the forbidden gap of GaSe is obtained. This work represents the first quantitative calculation of tunneling currents in a metal-insulator-metal structure with all parameters relevant to the experiment independently determined.</p>
https://resolver.caltech.edu/CaltechTHESIS:06112018-102411958Some Electronic Properties of ZnO and SrTiO₃
https://resolver.caltech.edu/CaltechTHESIS:06132018-121037092
Year: 1971
DOI: 10.7907/ZF7V-1G45
<p>The surface barrier systems consisting of gold and palladium on both chemically prepared and cleaved zinc oxide have been studied in detail.
Surface barrier energies on non-degenerate chemically prepared zinc oxide were found to be 0.66 and 0.60 eV respectively for gold and palladium, as determined by four independent methods: photoresponse, current-voltage characteristics, thermal activation energy, and capacitance variation with voltage. The Bethe diode theory as modified by image force lowering was found to be an excellent description of the voltage-current characteristics. Thermionic field and pure tunneling currents were observed for surface barriers on degenerate zinc oxide at room and liquid nitrogen temperatures, respectively. The voltage dependence of these currents was in excellent agreement with the thermionic field and tunneling theories. Although dependence on impurity concentration was functionally in agreement with theory the predicted currents were too high by an order of magnitude. This effect is attributed to deficiencies in the theory.</p>
<p>The second material investigated was strontium titanate. The surface barrier systems consisting of gold, palladium, copper, and indium on both chemically prepared and cleaved single crystal strontium titanate were examined in detail. Surface barrier energies were determined, and the current versus voltage characteristics were examined in light of Bethe diode theory as modified by image force lowering. The relative permittivity of strontium titanate was determined over a temperature range from
4.2<sup>°</sup>K to 300<sup>°</sup>K as a function of applied electrical bias. No evidence of a ferroelectric transition was observed. A phenomonological description of the free energy involved in the titanium atom motion, which is responsible for the large relative permittivity, was derived. Evidence for domain interaction is discussed.</p>
https://resolver.caltech.edu/CaltechTHESIS:06132018-121037092I. Fundamental Limitations in Microelectronics. II. Power Schottky Diode Design and Comparison with the Junction Diode. III. Permittivity of Strontium Titanate
https://resolver.caltech.edu/CaltechTHESIS:04182016-112301893
Year: 1972
DOI: 10.7907/TVY5-NY24
<p>Part I</p>
<p>The physical phenomena which will ultimately limit the packing density of planar bipolar and MOS integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum size of a bipolar transistor is determined by junction breakdown, punch-through and doping fluctuations. The minimum size of a MOS transistor is determined by gate oxide breakdown and drain-source punch-through. The packing density of fully active bipolar or static non-complementary MOS circuits becomes limited by power dissipation. The packing density of circuits which
are not fully active such as read-only memories, becomes limited by the area occupied by the devices, and the frequency is limited by the circuit time constants and by metal migration. The packing density of fully active dynamic or complementary MOS circuits is limited by the area occupied by the devices, and the frequency is limited by power dissipation and metal migration. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.</p>
<p>Part II</p>
<p>Because the Schottky diode is a one-carrier device, it has both advantages and disadvantages with respect to the junction diode which is a two-carrier device. The advantage is that there are practically no excess minority carriers which must be swept out before the diode blocks current in the reverse direction, i.e. a much faster recovery time. The disadvantage of the Schottky diode is that for a high voltage device it is not possible to use conductivity modulation as in the p i n diode; since charge carriers are of one sign, no charge cancellation can occur
and current becomes space charge limited. The Schottky diode design is developed in Section 2 and the characteristics of an optimally designed silicon Schottky diode are summarized in Fig. 9. Design criteria and quantitative comparison of junction and Schottky diodes is given in Table 1 and Fig. 10. Although somewhat approximate, the treatment allows a systematic quantitative comparison of the devices for any given application.</p>
<p>Part III</p>
<p>We interpret measurements of permittivity of perovskite strontium titanate as a function of orientation, temperature, electric field and frequency performed by Dr. Richard Neville. The free energy of the crystal is calculated as a function of polarization. The Curie-Weiss law and the LST relation are verified. A generalized LST relation is used to calculate the permittivity of strontium titanate from zero to
optic frequencies. Two active optic modes are important. The lower frequency mode is attributed mainly to motion of the strontium ions with respect to the rest of the lattice, while the higher frequency active mode is attributed to motion of the titanium ions with respect to the oxygen lattice. An anomalous resonance which multi-domain strontium titanate crystals exhibit below 65°K is described and a plausible mechanism which explains the phenomenon is presented.</p>
https://resolver.caltech.edu/CaltechTHESIS:04182016-112301893Electrical and Optical Properties of Beta-Gallium Oxide
https://resolver.caltech.edu/CaltechTHESIS:04042016-102655753
Year: 1972
DOI: 10.7907/HB9S-1F80
<p>An experimental investigation of the optical properties of β–gallium oxide has been carried out, covering the wavelength range 220-2500 nm. </p>
<p>The refractive index and birefringence have been determined to about ± 1% accuracy over the range 270-2500 nm, by the use of a technique based on the occurrence of fringes in the transmission of a thin sample due to multiple internal reflections in the sample (ie., the "channelled spectrum" of the sample.)</p>
<p>The optical absorption coefficient has been determined over the range 220 - 300 nm, which range spans the fundamental absorption edge of β – Ga<sub>2</sub>O<sub>3</sub>. Two techniques were used in the absorption coefficient determination: measurement of transmission of a thin sample, and measurement of photocurrent from a Schottky barrier formed on the surface of a sample. Absorption coefficient was measured over a range from 10 to greater than 10<sup>5</sup>, to an accuracy of better than ± 20%. The absorption edge was found to be strongly polarization-dependent.</p>
<p>Detailed analyses are presented of all three experimental techniques used. Experimentally determined values of the optical constants are presented in graphical form.</p>
https://resolver.caltech.edu/CaltechTHESIS:04042016-102655753Voltage Gateable Ionic Pores Induced by Alamethicin in Black Lipid Membranes
https://resolver.caltech.edu/CaltechETD:etd-08092006-125321
Year: 1973
DOI: 10.7907/2YFT-Q653
The strongly surface-active polypeptide antibiotic alamethicin (m.w. ~ 1700) interacts with artificial black lipid membranes to form voltage gateable ionic channels with five discrete conductance states. The channels fluctuate between these states with transition rates which depend little on the applied voltage. Within any conductance state, the behavior is approximately ohmic and similar to bulk solutions. When added on one side only, alamethicin confers upon a phosphatidyl-ethanolamine-decane black film a pronounced asymmetry. The alamethicin channels are only slightly ion selective, their rate of formation is strongly dependent on the alamethicin concentration, on the voltage across the membrane and on the ionic strengths.https://resolver.caltech.edu/CaltechETD:etd-08092006-125321Incomplete Charge Transfer in Overlapping Gates Charge Coupled Devices
https://resolver.caltech.edu/CaltechTHESIS:02012018-092625397
Year: 1973
DOI: 10.7907/CEG6-AR39
<p>We have developed a numerical simulation of the charge transfer
in the overlapping gates charge coupled devices. The transport
dynamics were analyzed in terms of thermal diffusion, self-induced
fields and fringing fields under all the relevant electrodes and the
interelectrode regions with time varying gate potentials. We have also
developed a lumped circuit model of charge coupled devices. Using
this model simple analytic expressions describing the charge transfer
with various clocking waveforms are derived. This model can be used
to study the charge transfer characteristics for other device structures,
dimensions, clocking waveforms and voltages, thus providing
practical charge coupled device and circuit design tools.</p>
<p>Using the numerical simulation and lumped circuit model, the
influence of clocking waveforms and clocking schemes on CCD operation
are studied. It is concluded that increasing the clocking scheme
complexity allows a better control of the storage and transfer of the
signal charge and hence improves the signal dynamic range and charge
transfer characteristics. It is shown that the performance of charge
coupled devices is better with push clocks (that push the charge from
one storage site to another) than with drop clocks (that create
deeper potential wells to transfer the charge). The performance of
charge coupled devices is shown to be basically superior to the MOS
bucket brigade.</p>
<p>We have also developed a simple model to study the incomplete
charge transfer due to trapping in the interface states. Incomplete
charge transfer due to trapping in interface states is shown to limit
the performance CCDs at low frequencies. The most dominant effect
is trapping in the interface states under the edges of the gates
parallel to the active channel. The influence of the device parameters,
dimensions and clocking waveforms on the signal degradation is discussed.
Design features of CCD structures which would reduce the
incomplete charge transfer due to interface states are presented. It
is shown that increasing the clock voltages, increasing the signal
charge or using dynamic push clock reduces the incomplete charge
transfer due to interface states.</p>
<p>The contents of this thesis have been published under the
following titles:</p>
<p>"Charge Transfer in Overlapping Gates Charge Coupled Devices"
A. M. Mohsen, T. C. McGill and C. A. Mead, Journal of Solid State
Circuits, SC-8, No. 3, June 1973.</p>
<p>"The Influence of Interface States on Incomplete Charge
Transfer in Overlapping Gates Charge Coupled Devices",
A. M. Mohsen, T. C. McGill , Y. Daimon and C. A. Mead,
Journal of Solid State Circuits, SC-8, No. 2, April 1973.</p>
<p>"Push Clocks: A new approach to charge coupled device
clocking", A. M. Mohsen, T. C. McGill, M. Anthony and
C. A. Mead, Appl. Phys. Letters, 22, 4, February 15, 1973,
pp. 172-175.</p>
<p>"Charge Transfer in Charge Coupled Devices", A. M. Mohsen,
T. C. McGill and C. A. Mead, ISSCC Digest of Technical Papers
15, 1972, pp. 248-249</p>
<p>The contents of this thesis have also been presented in the following
conferences:</p>
<p>"Physics of Charge Coupled Devices", Invited Review Talk
given at the Gordon Research Conference, Meriden, New
Hampshire, August 1972.</p>
<p>"The Influence of Clocking Waveforms of CCD Operation",
presented at the International Device Research Conference
at Edmonton, Canada, June 1972.</p>
<p>"Charge Transfer in Charge Coupled Devices", presented at
the International Solid State Circuits Conference,
Philadelphia, Pa., February 1972.</p>
<p>A motion picture simulation of the various stages of the charge transfer
process with two-phase and four-phase clocking schemes was produced
directly from the results of the numerical simulation developed in this
thesis. The CCD movie has been presented in the conferences mentioned
above and is included in the "Semiconductor Memory Course" prepared
by Texas Instruments on video tapes. The CCD movie is published in
the Journal of Solid State Circuits (June 1973) as three sequences of
page-flip movie.</p>
https://resolver.caltech.edu/CaltechTHESIS:02012018-092625397A 16-Bit LSI Digital Multiplier
https://resolver.caltech.edu/CaltechTHESIS:04122012-143452788
Year: 1978
DOI: 10.7907/64v1-br36
<p>Multiplication in digital machines is often done sequentially by the processor's arithmetic logic unit. However, this method is very time consuming due to the many sequential shifts and additions required. Implementing this multiplication directly with hardware increases speed, but at added cost. By implementing an interesting multiplication algorithm on an LSI chip, it is possible to achieve high performance with little added cost.</p>
<p>This paper describes a single chip LSI implementation of such a hardware multiplier. This multiplier/accumulator chip performs a fast multiplication of two 16 bit 2's complement words. It was designed and implemented in silicon gate NMOS with depletion loads. By using a multiple hit examination algorithm, the circuitry requirements were significantly less than that of a standard hardware multiplier. Also, by employing carry-save adders and carry lookahead logic, multiplication delay times are competitive with bipolar implementations, but require one-fifth the power.</p>
<p>An on-chip accumulator allows successive products to be summed without tying up the external data bus. Special completion sensing logic allows the chip to be used in asynchronous timing applications. The 16 bit by 16 bit multiplier chip measures 180 by 180 mils. All circuits are modular, and chips of arbitrary word size can be generated by changing only two parameter values during the computer aided mask layout generation process.</p>https://resolver.caltech.edu/CaltechTHESIS:04122012-143452788Investigations of the conductor-semiconductor interface
https://resolver.caltech.edu/CaltechTHESIS:07222014-101031867
Year: 1978
DOI: 10.7907/z9j6-a423
<p>I. Schottky barriers produced by polymeric sulfur nitride,
(SN)<sub>x</sub>, on nine common III-V and II-VI compound semiconductors
are compared to barriers formed by Au. The
conductor (SN)<sub>x</sub> produces significantly higher barriers to
n-type semiconductors and lower barriers to p-type semiconductors
than Au, the most electronegative elemental
metal. The barrier height improvement, defined as
ɸ(SN)<sub>x</sub> - ɸ(Au), is smaller on covalent semiconductors
than on ionic semiconductors; (SN)x barriers follow the
ionic-covalent transition. Details of (SN)<sub>x</sub> film deposition,
samples preparation, and barrier height measurements
are described.</p>
<p>II. The rate of dissolution of amorphous Si into solid
Al is measured. The rate of movement of the amorphous
Si/Al interface is found to be much faster than predicted
by a simple model of the transport of Si through Al.
This result is related to defects in the growth of epitaxial
Si using the solid phase epitaxy process.</p>https://resolver.caltech.edu/CaltechTHESIS:07222014-101031867I. A recirculating charged-couple device. II. The mercury selenide on N-silicon Schottky barrier
https://resolver.caltech.edu/CaltechTHESIS:07172014-100207238
Year: 1978
DOI: 10.7907/dadc-z725
<p>A recirculating charge-coupled device structure has
been devised. Entrance and exit gates allow a signal to be
admitted, recirculated a given number of times, and then
examined. In this way a small device permits simulation
of a very long shift register without passing the signal
through input and output diffusions. An oscilloscope
motion picture demonstrating degradation of an actual
circulating signal has been made. The performance of the
device in simulating degradation of a signal by a very long
shift register is well fit by a simple model based on
transfer inefficiency.</p>
<p>Electrical properties of the mercury selenide on
n-type chemically-cleaned silicon Schottky barrier have
been studied. Barrier heights measured were 0.96 volts
for the photoresponse technique and 0.90 volts for the
current-voltage technique. These are the highest barriers
yet reported on n-type silicon.</p>https://resolver.caltech.edu/CaltechTHESIS:07172014-100207238Understanding Hierarchical Design
https://resolver.caltech.edu/CaltechETD:etd-12062006-104710
Year: 1980
DOI: 10.7907/Z9BP00R2
With the exponential improvement in integrated circuit technology comes the problem of how to design systems containing millions of devices. This thesis presents a new look at hierarchical design based on the Caltech structured design methodology.
The hierarchy is separated into two parts: leaf cells, containing no instances of other cells, and composition cells, containing only instances of other cells. A leaf cell can be implemented in many different representations. A representation consists of a set of leaf cells and a composition rule that builds correct higher level cells.
The separated hierarchy is suitable for mathematical analysis by the use of Curry's theory of combinators. In this form, a hierarchy is represented by a mathematical operator that produces a digital system from the leaf cells. The question of hierarchical equivalence is examined.
Three sample composition rules, or algorithms, are presented as examples. The SLAP system provides a geometry composition rule that produces the mask description of a system given the geometries of the leaf cells. In analogy to TYPEing in a programming language, two representations that enforce a certain design style are discussed. The first TYPE system guarantees signal integrity. The second TYPE system guarantees mutual exclusion between the sources on a bus.https://resolver.caltech.edu/CaltechETD:etd-12062006-104710The Tree Machine: A Highly Concurrent Computing Environment
https://resolver.caltech.edu/CaltechETD:etd-12082006-153626
Year: 1980
DOI: 10.7907/15zs-9x82
An architecture for a VLSI multiprocessor machine is proposed. The processors are connected together as a binary tree. A collection of algorithms are mapped onto the tree machine. These include heap sort transitive closure, the travelling salesman, and matrix inversion, among others. A model of computational complexity for the tree machine is suggested, and the algorithms are analyzed in the context of that model. A notation for expressing the algorithms is described, a processor design is proposed, and a compiler for the notation and processor is presented.https://resolver.caltech.edu/CaltechETD:etd-12082006-153626Silicon Compilation
https://resolver.caltech.edu/CaltechETD:etd-11092006-140405
Year: 1981
DOI: 10.7907/32ha-8453
<p>Modern integrated circuits are among the most complex systems designed by man. Although we have seen a rapid increase in fabrication technology, traditional design methodologies have not evolved at a rate commensurate with the increasing design complexity potential. These circuit design methodologies fail when applied to Very Large Scale Integrated (VLSI) circuit design. This thesis proposes a new design methodology which manages the complexity VLSI design, allowing economical generation of correctly functioning circuits.</p>
<p>Cost is one measurement of a design methodology's value. A good design methodology rapidly and efficiently translates high level system specifications into working parts. Traditional techniques partition the translation process into many steps; each design tool is focused upon one of these design steps. This partitioning precludes the consideration of global constraints, and introduces a literal explosion of data being transfered between design steps. The design process becomes error-prone and time consuming.</p>
<p>The technique of silicon compilation presented in this thesis automatically translates from high level specifications into correct geometric descriptions. In this approach, the designer interacts at a high level of abstraction, and need not be concerned with lower levels of detail, facilitating exploration of alternate system architectures. Furthermore, since the implementation is algorithmically generated, chip descriptions can be made correct by construction. Finally, the user is given technology independence, because the high level specification need not require knowledge of fabrication details. This flexibility allows the user to take advantage of technology advances.</p>
<p>This thesis explores various aspects of silicon compilation, and presents a prototype compiler, Bristle Blocks. The methodology is demonstrated through the design of several chips. The practicality of the methodology results from the concern for efficiency of the design process and of the chip designs produced by the system.</p>https://resolver.caltech.edu/CaltechETD:etd-11092006-140405From Geometry to Logic
https://resolver.caltech.edu/CaltechTHESIS:04122012-091736952
Year: 1981
DOI: 10.7907/887g-zn84
<p>Transformation between five different intermediate forms used in VLSI design are discussed. The intermediate forms are: the D language, Akers' Diagrams, transistor listings, the sticks standard, and CIF language. They represent architecture, logic, transistor, topology and geometric levels, respectively. To understand more about the relationships between these levels, a series of transformations from the CIF to the sticks standard, from the sticks standard to the transistor listing, and from the transistor listing to the Akers' Diagram are presented. By doing this, the description gap between the logical world and the physical world is bridged.</p>
<p>CAD developers often complain about the lack of a model that can be applied uniformly throughout the entire design process. Akers' Diagrams seem to meet this demand. This work highlights this point.</p>
<p>As an example, a shift register implemented in NMOS technology will appear many times in this thesis.</p>https://resolver.caltech.edu/CaltechTHESIS:04122012-091736952Hybrid Processing
https://resolver.caltech.edu/CaltechETD:etd-09132006-131111
Year: 1982
DOI: 10.7907/ssgy-ep18
<p>The past decade has witnessed a revolution in digital electronics. As the cost per function has decreased, digital techniques have pushed the older analog methods into the background. This thesis explores a method of merging digital and analog techniques into a hybrid combination of the two. Representing the analog information as continuously variable intervals of time minimizes the effects of noise on the analog data. Ensuring that only digital data pass from one computation to another prevents the accumulation of errors.</p>
<p>As an example of hybrid processing, this thesis includes the design of Large Scale Integrated (LSI) circuit that implements the Lee-Moore maze solving algorithm, extended to cover the two-layer path finding case. The use of digital information to describe the path geometry and analog information to describe the path costs demonstrates the system's hybrid nature.</p>
<p>The design of this system provided several lessons applicable to the design of other hybrid systems. It also unexpectedly demonstrated the importance of the communication structure in determining the costs involved in all kinds of processing. These lessons are summarized in the last chapter.</p>https://resolver.caltech.edu/CaltechETD:etd-09132006-131111VLSI Computational Structures Applied to Fingerprint Image Analysis
https://resolver.caltech.edu/CaltechTHESIS:03202012-091934255
Year: 1983
DOI: 10.7907/9tyn-bc11
<p>Advances in integrated circuit technology have made possible the application of LSI and VLSI techniques to a wide range of computational problems. Image processing is one of the areas that stands to benefit most from these techniques. This thesis presents an architecture suitable for VLSI implementations which enables a wide range of image processing operations to be done in a real-time, pipelined fashion. These operations include filtering, thresholding, thinning and feature extraction.</p>
<p>The particular class of images chosen for study are fingerprints. There exists a long history of fingerprint classification and comparison techniques used by humans, but previous attempts at automation have met with little success. This thesis makes use of VLSI image processing operations to create a graph structure representation (minutia graph) of the inter-relationships of various low-level features of fingerprint images. An approach is then presented which allows derivation of a metric for the similarity of these graphs and of the fingerprints which they represent. An efficient algorithm for derivation of maximal common subgraphs of two minutia graphs serves as the basis for computation of this metric, and is itself based upon a specialized clique-finding algorithm. Results of cross comparison of fingerprints from multiple individuals are presented.</p>https://resolver.caltech.edu/CaltechTHESIS:03202012-091934255Space-time Algorithms: Semantics and Methodology
https://resolver.caltech.edu/CaltechETD:etd-08312006-094203
Year: 1983
DOI: 10.7907/bfpj-t811
<p>A methodology for specifying concurrent systems is presented. A model of computation for concurrent systems is presented first. The syntax and semantics of the language CRYSTAL are introduced. The specification of a system is called a space-time algorithm since space and time are explicit parameters in the description. Fixed-point semantics is used for abstracting the behavior of a system from its implementation. The consistency between an implementation and its description can therefore be ensured using this method. Formal semantics for an arbitrary transistor network is given. An "interpreter" for space-time algorithms -- a hierarchical simulator -- for VLSI systems is presented. The framework can be viewed as a concurrent programming notation when describing communicating processes and as a hardware description notation when specifying integrated circuits.</p>https://resolver.caltech.edu/CaltechETD:etd-08312006-094203Hardware Support for Advanced Data Management Systems
https://resolver.caltech.edu/CaltechETD:etd-08102006-083426
Year: 1983
DOI: 10.7907/BH0Y-Q162
This thesis considers the problem of the optimal hardware architecture for advanced data management systems, of which the REL system can be considered a prototype. Exploration of the space of architectures requires a new technique which applies widely varying work loads, performance constraints, and heuristic configuration rules with an analytic queueing network model to develop cost functions which cover a representative range of organizational requirements. The model computes cost functions, which are the ultimate basis for comparison of architectures, from a technology forecast. The discussion shows the application of the modeling technique to thirty trial architectures which reflect the major classifications of data base machine architectures and memory technologies. The results suggest practical design considerations for advanced data management systems.https://resolver.caltech.edu/CaltechETD:etd-08102006-083426Sequential Threshold Circuits
https://resolver.caltech.edu/CaltechTHESIS:04122012-104617758
Year: 1985
DOI: 10.7907/fsx9-vh16
No abstract.https://resolver.caltech.edu/CaltechTHESIS:04122012-104617758Hierarchical Composition of VLSI Circuits
https://resolver.caltech.edu/CaltechETD:etd-03242008-112135
Year: 1985
DOI: 10.7907/ykeb-r680
<p>A transistor level representation for VLSI circuits is presented. This representation is simple but general, technology independent, hierarchical, and maintains connectivity, circuit schematic information, and the information for mask geometry.</p>
<p>A transistor level cell is represented as the interconnection of devices along with their types, sizes and placement, and the cell's typed ports. Connection is represented explicitly by shared connection points. The ports describe the interface between this cell and other cells. This representation, together with a set of synthesis and analysis rules, enforces the description of strictly legal designs. The synthesis rules ensure that each structure is correct by construction. The analysis rules check for geometrical design rule violations which cannot, by their nature, be enforced by construction.</p>
<p>A file of technology dependent information indicates how to implement each transistor type, interconnect type and connection point type, as well as how structure types may interact.</p>
<p>Cells described in this representation may be composed hierarchically to form larger cells. Given a valid composition, the topology, geometry and connectivity of the composite structure is guaranteed to be legal.</p>
<p>A working system supporting this hierarchical representation is also described. This system currently supports design rules for nMOS and cMOS/bulk, and has produced chip descriptions that have been both fabricated and tested.</p>https://resolver.caltech.edu/CaltechETD:etd-03242008-112135A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems
https://resolver.caltech.edu/CaltechETD:etd-04102008-105646
Year: 1985
DOI: 10.7907/41bh-7e43
<p>A hierarchical timing simulation model for digital MOS circuits and systems is presented. This model supports the structured design methodology, and can be applied to both "structure" and "behavior" representations of designs in a uniform manner. A simulator based on this model can run several orders of magnitude faster than any other simulators that offer the same amount of information.</p>
<p>At the structure (transistor) level, the transient behavior of a digital MOS circuit is approximated by that of an RC network for estimating delays. The Penfield-Rubinstein RC tree model is extended to include the effects of parallel paths and initial charge distributions. As far as delay is concerned, a two-port RC network is characterized by three parameters: R: series resistance, C: loading capacitance and D: internal delay. These parameters can be determined hierarchically as networks are composed in various ways. The composition rules are derived directly from the Kirchoff's current and voltage laws, so that the consistency with physics is established.</p>
<p>The (R, C, D) characterization of two-port RC networks is then generalized to describe the behavior of semantic cells at any level of representation. A semantic cell is a functional block which can be abstracted by its steady-state behavior to interface with other cells in the system. As semantic cells are composed, the parameters of the composite cell can be determined from those of the the component cells either analytically or by simulation. A Smalltalk implementation of the hierarchical timing simulation model is also presented.</p>https://resolver.caltech.edu/CaltechETD:etd-04102008-105646anaLOG: A functional Simulator for VLSI Neural Systems
https://resolver.caltech.edu/CaltechTHESIS:04112012-092513753
Year: 1986
DOI: 10.7907/af3r-e056
No abstract.https://resolver.caltech.edu/CaltechTHESIS:04112012-092513753Integrated Optical Motion Detection
https://resolver.caltech.edu/CaltechETD:etd-03102008-081506
Year: 1986
DOI: 10.7907/PK3H-CM61
<p>Two systems for detecting the motion of a scene are described. For both, an image is projected directly onto an integrated circuit that contains photosensors and computing circuitry to extract the motion. The first system, which has been reported earlier, correlates the analog image with a digitized version of the image stored from the previous cycle. The chip reports the motion that corresponds to the maximum analog correlation value. This system represents an advance from previous designs but exhibits some shortcomings.</p>
<p>A second completely analog design surpasses the first. The mathematical foundation is derived and the CMOS circuits used in the implementation are given. Test results and characterization of the working chips are reported. The new motion detector is not clocked and exhibits collective behavior. The use of local information extensively avoids the correspondence problem. The system can be thought of as a Hopfield neural net with one important extension—input driven synapses. The motion detector also meshes nicely with the existing computational vision work. Extensions to handle more complex motions are proposed. The suitability of the motion extraction algorithm as a biological vision model is explored.</p>https://resolver.caltech.edu/CaltechETD:etd-03102008-081506VLSI Concurrent Computation for Music Synthesis
https://resolver.caltech.edu/CaltechETD:etd-03052008-112515
Year: 1987
DOI: 10.7907/qjfp-m864
<p>This thesis presents a very large-scale integrated circuit (VLSI) approach to the generation of musical sounds. The approach allows the generation of rich musical sounds using models that are easy to control and have parameters corresponding to many of the physical attributes of musical instruments. The generality of the approach for music synthesis is demonstrated by presenting several primitive sound generation mechanisms. Utilizing these primitives, several musical instruments are assembled to produce struck, plucked, and blown sounds. Refinements of the instruments are easily accomplished by adjusting or rearranging different functional components. A concurrent computing engine supporting the sound generation mechanisms is presented along with details of its VLSI implementation. Involved in the implementation is a new CMOS design methodology. Several alternative architectures for the computing engine are also presented and studied.</p>https://resolver.caltech.edu/CaltechETD:etd-03052008-112515A Charge-Controlled Model for MOS Transistors
https://resolver.caltech.edu/CaltechETD:etd-02082007-135328
Year: 1989
DOI: 10.7907/JHQE-T452
<p>As MOS (metal-oxide-semiconductor) devices scale to submicron lengths, short-channel effects begin to dominate device behavior, and designers of VLSI (very-large-scale-integrated) circuits see an improved transistor model as a necessary tool. A new physically based, charge-controlled model for the DC current, the intrinsic terminal charges, and the transcapacitances in the MOS transistor under quasistatic conditions has been developed. The model expresses the current in the MOS transistor in terms of the mobile charge per unit area in the channel, and uses a complete set of natural units for velocity, voltage, length, charge, and current. The current-flow equation for the transistor includes both a drift term and a diffusion term, so that the formulation applies equally over the subthreshold, saturation, and "ohmic" regions of transistor operation and includes the effect of velocity saturation. The solution of this dimensionless current-flow equation using these units is a simple, continuous expression, and is suitable for the computer simulation of integrated circuits. The expression allows the regimes of transistor operation and the behavior of long-channel devices versus short-channel devices to be discerned easily. In particular, the expressions for source and drain terminal charges combine the mobile charge in the channel at the source and drain ends in simple polynomials. Analysis of the model shows a fundamental relation between the transistor transcapacitances and transconductances, and permits the development of efficient simulation models of them.</p>
<p>Our physically based transistor model uses parameters derived from the fabrication process by direct measurement and from the dimensions of the device. The zero-order model agrees closely with measurements on the scaling of current with channel length down to submicron channel lengths. For more detailed analog simulations, the model contains several first-order effects calculated as perturbations on the simple model. Comparisons among calculated and measured curves of conductance, capacitance, and drain currents demonstrate the accuracy of the model both above and below threshold for a number of experimental devices of different channel lengths. Results from the model concur with measurements on short-channel transistors down to 0.6-micron channel length. Several analog circuit simulators now contain the model.</p>https://resolver.caltech.edu/CaltechETD:etd-02082007-135328Silicon Models of Early Audition
https://resolver.caltech.edu/CaltechETD:etd-05152007-085000
Year: 1990
DOI: 10.7907/nt1w-ry58
This dissertation describes silicon integrated circuits that model known and proposed physiological structures in the early auditory system. Specifically, it describes silicon models of auditory-nerve response, of auditory localization in the barn owl, and of pitch perception. The integrated circuits model the structure as well as the function of the physiology; all subcircuits in the chips have anatomical correlates. The chips, two of which contain over 100,000 transistors, compute all outputs in real time, using analog, continuous-time processing. In most respects, chip responses approximate physiological or psychophysical response of the modeled biological systems. The dissertation also describes a novel nonlinear-inhibition circuit, which is a key component of two of the silicon models.
https://resolver.caltech.edu/CaltechETD:etd-05152007-085000An Object-Oriented Real-Time Simulation of Music Performance Using Interactive Control
https://resolver.caltech.edu/CaltechETD:etd-08102006-081706
Year: 1991
DOI: 10.7907/cy26-vp85
This thesis presents a software architecture for interactive control of real-time music performance by sound synthesizers. The architecture is based on a model of a real world orchestra performance. An object-oriented paradigm is used to define objects that are one-to-one with the real world entities: a conductor, performers, instruments, a score, and parts. Methods are defined for the objects to simulate some of the dynamic behavior of the conductor and performers during the performance. A detailed design of each of the objects is presented, and the objects and their real world counterparts are compared. An abstract digital music representation is defined to represent the musical composition that is to be performed by the system. The device independence of the representation is highlighted. A real-time control mechanism is described that allows a human user to control various aspects of the performance in musically expressive ways. The model is implemented in a system called ZED, which has been shown to simulate some of the dynamic behavior of a live orchestra. Issues concerning the trade-off between runtime efficiency and runtime flexibility are addressed in detail, as well as how these issues affect real-time scheduling. Optimization techniques are presented that help insure timeliness. ZED provides two levels of programmability: the orchestration of a score and the interpretation of real-time inputs can be defined in a configuration file; and new methods and subclasses can be added to the system to provide new functionality. The architecture, coupled with the object-oriented features of inheritance and encapsulation, are shown to provide the system with flexibility and extensibility, making ZED an ideal platform for developing and evolving real-time interactive control applications.https://resolver.caltech.edu/CaltechETD:etd-08102006-081706Analog VLSI Circuits for Sensorimotor Feedback
https://resolver.caltech.edu/CaltechETD:etd-06212007-074949
Year: 1991
DOI: 10.7907/vvye-b883
This thesis presents a design framework and circuit implementations for integrating sensory and motor processing onto very large-scale integrated (VLSI) chips. The designs consist of analog circuits that are composed of bipolar and subthreshold MOS transistors. The primary emphasis in this work is the transformation from the spatially-encoded representation found in sensory images to a scalar representation that is useful for controlling motor systems.
The thesis begins with a discussion of the aggregation of sensory signals and the resulting extraction of high-level features from sensory images. An integrated circuit that computes the centroid of a visual image is presented. A theoretical analysis of the function of this circuit in stimulus localization and a detailed error analysis are also presented. Next, the control of motors using pulse trains is discussed. Pulse-generating circuits for use in bidirectional motor control and the implementation of traditional control schemes are presented. A method for analyzing the operation of these controllers is also discussed. Finally, a framework for the combination of sensory aggregation and pulse-encoded outputs is presented. The need for signal normalization and circuits to perform this task are discussed. Two complete sensorimotor feedback systems are presented.https://resolver.caltech.edu/CaltechETD:etd-06212007-074949An Object-Oriented Real-Time Simulation of Music Performance Using Interactive Control
https://resolver.caltech.edu/CaltechETD:etd-08102006-081706
Year: 1991
DOI: 10.7907/cy26-vp85
This thesis presents a software architecture for interactive control of real-time music performance by sound synthesizers. The architecture is based on a model of a real world orchestra performance. An object-oriented paradigm is used to define objects that are one-to-one with the real world entities: a conductor, performers, instruments, a score, and parts. Methods are defined for the objects to simulate some of the dynamic behavior of the conductor and performers during the performance. A detailed design of each of the objects is presented, and the objects and their real world counterparts are compared. An abstract digital music representation is defined to represent the musical composition that is to be performed by the system. The device independence of the representation is highlighted. A real-time control mechanism is described that allows a human user to control various aspects of the performance in musically expressive ways. The model is implemented in a system called ZED, which has been shown to simulate some of the dynamic behavior of a live orchestra. Issues concerning the trade-off between runtime efficiency and runtime flexibility are addressed in detail, as well as how these issues affect real-time scheduling. Optimization techniques are presented that help insure timeliness. ZED provides two levels of programmability: the orchestration of a score and the interpretation of real-time inputs can be defined in a configuration file; and new methods and subclasses can be added to the system to provide new functionality. The architecture, coupled with the object-oriented features of inheritance and encapsulation, are shown to provide the system with flexibility and extensibility, making ZED an ideal platform for developing and evolving real-time interactive control applications.https://resolver.caltech.edu/CaltechETD:etd-08102006-081706Wiring Considerations in Analog VLSI Systems, with Application to Field-Programmable Networks
https://resolver.caltech.edu/CaltechETD:etd-07122007-134330
Year: 1991
DOI: 10.7907/stj4-kh72
This thesis develops a theoretical model for the wiring complexity of wide classes of systems, relating the degree of connectivity of a circuit to the dimensionality of its interconnect technology. This model is used to design an efficient, hierarchical interconnection network capable of accommodating large classes of circuits. Predesigned circuit elements can be incorporated into this hierarchy, permitting semi-customization for particular classes of systems (e.g., photoreceptors included on vision chips). A polynomial-time programming algorithm for embedding the desired circuit graph onto the prefabricated routing resources is presented, and is implemented as part of a general design tool for specifying, manipulating and comparing circuit netlists.
This thesis presents a system intended to facilitate analog circuit design. At its core is a VLSI chip that is electrically configured in the field by selectively connecting predesigned elements to form a desired circuit, which is then tested electrically. The system may be considered a hardware accelerator for simulation, and its large capacity permits testing system ideas, which is impractical using current means. A fast-turnaround simulator permitting rapid conception and evaluation of circuit ideas is an invaluable aid to developing an understanding of system design in a VLSI context.
We have constructed systems using both reconfigurable interconnection switches and laser-programmed interconnect. Prototypes capable of synthesizing circuits consisting of over 1000 transistors have been constructed. The flexibility of the system has been demonstrated, and data from parametric tests have proven the validity of the approach.
Finally, this thesis presents several new circuits that have become key components in many analog VLSI systems. Fast, dense and provably safe one-phase latches and hierarchical arbiters are presented, as are a low-noise analog switch, an isotropic novelty filter, a dense, active high-resistance element, and a subthreshold differential amplifier with a large linear input range.https://resolver.caltech.edu/CaltechETD:etd-07122007-134330VLSI Analogs of Neuronal Visual Processing: A Synthesis of Form and Function
https://resolver.caltech.edu/CaltechTHESIS:09122011-094355148
Year: 1992
DOI: 10.7907/4bdw-fg34
This thesis describes the development and testing of a simple visual system fabricated using complementary metal-oxide-semiconductor (CMOS) very large scale integration
(VLSI) technology. This visual system is composed of three subsystems. A silicon retina, fabricated on a single chip, transduces light and performs signal processing in a manner similar to a simple vertebrate retina. A stereocorrespondence chip uses bilateral retinal input to
estimate the location of objects in depth. A silicon optic nerve allows communication between chips by a method that preserves the idiom of action potential transmission in the
nervous system. Each of these subsystems illuminates various aspects of the relationship between VLSI analogs and their neurobiological counterparts. The overall
synthetic visual system demonstrates that analog VLSI can capture a significant portion of the function of neural structures at a systems level, and concomitantly, that incorporating neural architectures leads to new engineering approaches to computation in VLSI. The relationship
between neural systems and VLSI is rooted in the shared limitations imposed by computing in similar physical media. The systems discussed in this text support the belief that the physical limitations imposed by the computational medium significantly affect the evolving algorithm. Since circuits are essentially physical structures, I advocate the use of analog VLSI as powerful medium of abstraction, suitable for understanding and expressing the function of real neural systems. The working chip elevates the circuit description to a kind of synthetic formalism. The behaving physical circuit provides a formal test of theories of
function that can be expressed in the language of circuits.
https://resolver.caltech.edu/CaltechTHESIS:09122011-094355148Parallel Analog Computation with Charge Coupled Devices
https://resolver.caltech.edu/CaltechETD:etd-08312007-094832
Year: 1993
DOI: 10.7907/3e7h-9p50
Many signal processing and neural network algorithms can be mathematically described in terms of vector matrix multiplication. This thesis introduces two new architectures for computing high-speed vector matrix multiplication using charge coupled devices. These integrated circuits have been designed to accept optical matrix input as well as direct electrical matrix input. In both architectures, the matrix elements are stored as analog charge packets in CCD wells while the vectors are communicated to and from the integrated circuits by electrical means.
The first architecture accomplishes the vector matrix product using a semiparallel computation scheme that requires N clock cycles of the device to complete one vector matrix multiplication where N is the length of the input vector. An analysis of the linearity and charge transfer induced errors is given. The circuit represents an advance over other analog signal processors in density and speed but has serious shortcomings in accuracy, particularly the limited precision of the input vectors.
The second architecture is based on charge injection device (CID) imager arrays and addresses many of the inadequacies of the semiparallel architecture. A fully parallel circuit, the CID has similar density and much higher computation speed and accuracy. A novel digital input method is introduced that extends the input vector precision significantly. In addition, accuracy issues related to charge transfer efficiency are resolved. An analysis of linearity and accuracy is provided showing the advantages of the architecture over previous implementations.https://resolver.caltech.edu/CaltechETD:etd-08312007-094832Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks
https://resolver.caltech.edu/CaltechETD:etd-08292007-104823
Year: 1993
DOI: 10.7907/1ykm-yq27
This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process.
To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation.
Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for quantitative computation, as well as qualitative.https://resolver.caltech.edu/CaltechETD:etd-08292007-104823Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks
https://resolver.caltech.edu/CaltechETD:etd-08292007-104823
Year: 1993
DOI: 10.7907/1ykm-yq27
This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process.
To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation.
Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for quantitative computation, as well as qualitative.https://resolver.caltech.edu/CaltechETD:etd-08292007-104823Investigations of analog VLSI visual transduction and motion processing
https://resolver.caltech.edu/CaltechETD:etd-07022004-144710
Year: 1993
DOI: 10.7907/N5TD-G224
This thesis is a detailed description of a neuromorphic visual-motion processing chip and its component parts. The chip is the first two-dimensional silicon retina with a full set of direction-selective, velocity-tuned pixels. The architecture for the chip is based on the biological correlation-type motion detector, with the addition of a novel spatiotemporal aggregation. All the processing on the chip is analog and occurs in parallel. Novel, on-chip, continuous-time, adaptive, logarithmic photoreceptor circuits are used to couple temporal image signals into the motion processing network. These continuous-time photoreceptor circuits have also been used in a wide variety of other vision chips. The photoreceptor circuits center their operating point around the history of the illumination, simultaneously achieving high sensitivity and wide dynamic range. The receptor circuits are characterized and analyzed carefully for their temporal bandwidth and detection performance. Noise properties are analyzed, resulting in a simple and intuitive understanding of the limiting parameters. Novel adaptive elements are described that are insensitive to light-generated minority carriers. Novel measurements are presented of the spectral response properties of phototransducers that can be built in ordinary CMOS or BiCMOS processes. A novel nonlinear circuit that measures similarity and dissimilarity of signals is described and characterized. These bump circuits are used on the motion chip to extract the motion energy signal, and have also been used in other chips in numerous ways.https://resolver.caltech.edu/CaltechETD:etd-07022004-144710Cochlear Mechanics: Analysis and Analog VLSI
https://resolver.caltech.edu/CaltechETD:etd-07022004-115127
Year: 1993
DOI: 10.7907/19EW-YM12
<p>The cochlea separates sounds based on their frequency content and on their fine time structure, using an active and nonlinear fluid-mechanical traveling-wave mechanism. This dissertation describes a simplified model of the cochlear mechanics problem, and techniques for solving the problem.</p>
<p>The Liouville-Green (LG) method has been used to obtain analytical solutions for the cochlear mechanics problem; however, the failure of the method to agree quantitatively with numerical methods has left doubts about its validity. In this dissertation, it is shown that the LG method fails to solve the problem, and that an additional degree of freedom is required for a consistent solution. The additional degree of freedom corresponds to a second wave mode, which has been observed experimentally in the cochleas of living animals. The new mode-coupling LG solution agrees quantitatively with numerical solutions. This problem has been outstanding since 1971.</p>
<p>In addition to analytical techniques, this dissertation also presents analog circuit techniques, specifically for the medium of analog very-large-scale-integration (VLSI) complementary metal-oxide-semiconductor (CMOS) technology. A silicon cochlea that models the behavior of the passive cochlea has been fabricated and tested. The silicon cochlea operates in real time with 8 mW of power dissipation.</p>
<p>The active and nonlinear behavior of the cochlea is a subject of intense research interest at the present time, and many issues are still unresolved. A preliminary model of active elements in the cochlea is described and characterized, and shown to be consistent with the prevailing views of active cochlear function.</p>https://resolver.caltech.edu/CaltechETD:etd-07022004-115127Parallel Analog Computation with Charge Coupled Devices
https://resolver.caltech.edu/CaltechETD:etd-08312007-094832
Year: 1993
DOI: 10.7907/3e7h-9p50
Many signal processing and neural network algorithms can be mathematically described in terms of vector matrix multiplication. This thesis introduces two new architectures for computing high-speed vector matrix multiplication using charge coupled devices. These integrated circuits have been designed to accept optical matrix input as well as direct electrical matrix input. In both architectures, the matrix elements are stored as analog charge packets in CCD wells while the vectors are communicated to and from the integrated circuits by electrical means.
The first architecture accomplishes the vector matrix product using a semiparallel computation scheme that requires N clock cycles of the device to complete one vector matrix multiplication where N is the length of the input vector. An analysis of the linearity and charge transfer induced errors is given. The circuit represents an advance over other analog signal processors in density and speed but has serious shortcomings in accuracy, particularly the limited precision of the input vectors.
The second architecture is based on charge injection device (CID) imager arrays and addresses many of the inadequacies of the semiparallel architecture. A fully parallel circuit, the CID has similar density and much higher computation speed and accuracy. A novel digital input method is introduced that extends the input vector precision significantly. In addition, accuracy issues related to charge transfer efficiency are resolved. An analysis of linearity and accuracy is provided showing the advantages of the architecture over previous implementations.https://resolver.caltech.edu/CaltechETD:etd-08312007-094832The Central Nervous Control of Walking in the Locust Schistocerca americana
https://resolver.caltech.edu/CaltechTHESIS:04112013-092807415
Year: 1994
DOI: 10.7907/1aey-8096
<p>Rhythmic motor behaviors in all animals appear to be under the control of "central pattern generator" circuits, neural circuits which can produce output patterns appropriate for behavior even when isolated from their normal peripheral inputs. Insects have been a useful model system in which to study the control of legged terrestrial locomotion. Much is known about walking in insects at the behavioral level, but to date there has been no clear demonstration that a central pattern generator for walking exists. The focus of this thesis is to explore the central neural basis for locomotion in the locust, Schistocerca americana.</p>
<p>Rhythmic motor patterns could be evoked in leg motor neurons of isolated thoracic ganglia of locusts by the muscarinic agonist pilocarpine. These motor patterns would be appropriate for the movement of single legs during walking. Rhythmic patterns could be evoked in all three thoracic ganglia, but the segmental rhythms differed in their sensitivities to pilocarpine, their frequencies, and the phase relationships of motor neuron antagonists. These different patterns could be generated by a simple adaptable model circuit, which was both simulated and implemented in VLSI hardware. The intersegmental coordination of leg motor rhythms was then examined in preparations of isolated chains of thoracic ganglia. Correlations between motor patterns in different thoracic ganglia indicated that central coupling between segmental pattern generators is likely to contribute to the coordination of the legs during walking.</p>
<p>The work described here clearly demonstrates that segmental pattern generators for walking exist in insects. The pattern generators produce motor outputs which are likely to contribute to the coordination of the joints of a limb, as well as the coordination of different limbs. These studies lay the groundwork for further studies to determine the relative contributions of central and sensory neural mechanisms to terrestrial walking.</p>
https://resolver.caltech.edu/CaltechTHESIS:04112013-092807415Analysis, synthesis, and implementation of networks of multiple-input translinear elements
https://resolver.caltech.edu/CaltechETD:etd-01162008-075623
Year: 1997
DOI: 10.7907/rh58-rz05
At the time of its invention in the seventeenth century, the logarithmic slide rule literally revolutionized the way calculation was done. From then until the advent of the pocket calculator, this analog computational device was widely used to perform multiplications and divisions, to raise numbers to fixed powers and extract fixed roots of numbers. Today, the slide rule may be gone, but it is not forgotten. In this thesis, I present a class of simple translinear network circuits which essentially function as electronic slide rules, accurately computing products, quotients, powers, and roots. I describe two different analysis procedures that allow us to determine the steady-state relationship between input and output currents. I also describe systematic techniques for synthesizing such circuits whereby we can produce a circuit whose steady-state transfer characteristics embody some desired product-of-power-law relationship between input and output currents. These circuits are made from multiple-input translinear elements; such elements produce output currents that are proportional to the exponential of a weighted sum of their input voltages. We can implement the weighted voltage summations with either resistive or capacitive voltage dividers. We can obtain the required exponential voltage-to-current transformations from either bipolar transistors or subthreshold MOS transistors. The subthreshold floating-gate MOS transistor naturally implements the exponential-of-a-weighted-sum operation in a single device. I will present experimental results from several of these translinear network circuits breadboarded from subthreshold floating-gate MOS transistors. I will also describe and present experimental data from a variety of other implementations of the multiple-input translinear element.https://resolver.caltech.edu/CaltechETD:etd-01162008-075623Efficient precise computation with noisy components : extrapolating from an electronic cochlea to the brain
https://resolver.caltech.edu/CaltechETD:etd-08092005-104717
Year: 1997
DOI: 10.7907/FSBH-QA93
Low-power wide-dynamic-range systems are extremely hard to build. The cochlea is one of the most awesome examples of such a system: It can sense sounds over 12 orders of magnitude in intensity, with an estimated power dissipation of only a few tens of microwatts.
We describe an analog electronic cochlea that processes sounds over 6 orders of magnitude in intensity, while dissipating less than 0.5mW. This 117-stage, 100Hz-10Khz cochlea has the widest dynamic range of any artificial cochlea built to date. This design, using frequency-selective gain adaptation in a low-noise traveling-wave amplifier architecture, yields insight into why the human cochlea uses a traveling-wave mechanism to sense sounds, instead of using bandpass filters.
We propose that, more generally, the computation that is most efficient in its use of resources is an intimate hybrid of analog and digital computation. For maximum efficiency, the information and information-processing resources of the hybrid form of computation must be distributed over many wires, with an optimal signal-to-noise ratio per wire. These results suggest that it is likely that the brain computes in a hybrid fashion, and that an underappreciated and important reason for the efficiency of the human brain, which only consumes 12W, is the hybrid and distributed nature of its architecture.https://resolver.caltech.edu/CaltechETD:etd-08092005-104717Foundations of learning in analog VLSI
https://resolver.caltech.edu/CaltechETD:etd-06062005-155140
Year: 1997
DOI: 10.7907/2J7M-GE02
NOTE: Text or symbols not renderable in plain ASCII are indicated by [...]. Abstract is included in .pdf document.
Floating-gate technology can be used to build silicon systems that adapt and learn. This technology is well suited to implement adaptation and learning because we are not building analog EEPROMS, but rather circuit elements with important time domain dynamics. These floating-gate circuits use the hot-electron-injection, electron-tunneling, and drain-induced-barrier-lowering phenomena in a standard submicron CMOS process. This technology works with the constraints of the silicon medium, and is similar to biological systems that turned potential liabilities into features.
I develop the first analytical model of the impact-ionization and hot-electron processes in MOS devices by solving for a self-consistent distribution function from the spatially varying Boltzmann transport equation. From this electron distribution function, the probabilities of impact ionization and hot-electron injection are calculated as functions of channel current, drain voltage, and floating-gate voltage. The analytical model simultaneously fits both the hot-electron-injection and impact-ionization data. These analytical results yield measurements of the energy-dependent impactionization collision rate that is consistent with numerically calculated collision rates reported in the literature.
I describe the design, fabrication, characterization, and modeling of an array of single-transistor synapses that simultaneously store the weight value, compute the product of the input and floating gate value, and update the weight value according to a hebbian or backpropagation learning rule. Circuits with one floating-gate synapse exhibit a range of possible stabilizing and destabilizing behaviors, and circuits with multiple-synapses show examples of competitive and cooperative behavior. By providing feedback to the source, we get a [...]FET synapse where voltage changes in both the floating gate and drain stabilize the floating gate.
I present a bandpass floating gate amplifier that uses tunneling and [...]FET hot-electron injection to adaptively set its DC operating point. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high frequency cutoff is controlled electronically, as is done in continuous-time filters. I have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and input waveforms. This autozeroing floating-gate amplifier demonstrates how to use continuous-time, floating-gate adaptation.https://resolver.caltech.edu/CaltechETD:etd-06062005-155140Neuromorphic models of visual and motion processing in the fly visual system
https://resolver.caltech.edu/CaltechETD:etd-01152008-133452
Year: 1997
DOI: 10.7907/kxfr-s226
Since the first neuromorphic retina was introduced 10 years ago, we have seen neuromorphic modeling extended to motion processing, saccadic systems, and auditory processing, to name a few. This dissertation extends neuromorphic modeling to the fly visual system. The retinotopic and regular arrangement of the layers in this system makes viable the mapping of the structure of the layers to silicon. The ability of the fly to compute motion reliably with only 24,000 receptors, while consuming only microwatts of power, also makes this system attractive for neuromorphic modeling. I start this dissertation by comparing the filter bandwidth properties and offsets of the fly receptors with those of silicon receptors. The filtering properties and the offsets of the receptors are critical because they determine the limits of subsequent processing circuitry. This work is the first characterization of biological and artificial offsets. Next, I describe an analog circuit that captures some of the adaptation and temporal filtering properties of the cells in the initial layers of the visual system. The adaptation time constant of the circuit is controllable via an external bias. The temporal filtering of the circuit changes with the S/N ratio of signals. This prefiltering preceding the motion areas is important to ensure that the motion computation is robust under different S/N rations. The filtering should be adaptive to match the S/N ratio so as to maximise the information transfer to subsequent processing. Adaptation is also a big component of the motion computation since the visual system has to extract information from a 2 to 3 decade range of speeds of objects under a six decade range of illumination. In this dissertation, I show the first adaptive motion model that matches its time scale to that of the moving image. The model explains experimental data showing motion adaptation in the direction-selective cells of the fly. Finally, I describe the responses of the direction-selective cells to motion. This silicon model is critical in showing that local direction selectivity can be computed from the correlation of continuous-time, graded inputs. The computation integrates the visual information over time in the decision making process and binarized features are not needed for the correlation. This model differs from previous silicon implementations of the Reichardt model that used token-based information for correlation. This model is a closer analogue of the motion computation in flies than previous silicon models.https://resolver.caltech.edu/CaltechETD:etd-01152008-133452Neurally inspired silicon learning : from synapse transistors to learning arrays
https://resolver.caltech.edu/CaltechETD:etd-01092008-080326
Year: 1997
DOI: 10.7907/vbyq-fy15
A computation is an operation that can be performed by a physical machine. We are familiar with digital computers: Machines based on a simple logic function (the binary NOR) and optimized for manipulating numeric variables with high precision. Other computing machines exist: The neurocomputer, the analog computer, the quantum computer, and the DNA computer all are known. Neurocomputers-defined colloquially as computing machines comprising nervous tissue-exist; that they are computers also is certain. Nervous tissue solves ill-posed problems in real time. The principles underlying neural computation, however, remain for now a mystery.
I believe that there are fundamental principles of computation that we can learn by studying neurobiology. If we can understand how biological information-processing systems operate, then we can learn how to build circuits and systems that deal naturally with real-world data. My goal is to investigate the organizational and adaptive principles on which neural systems operate, and to build silicon integrated circuits that compute using these principles. I call my approach silicon neuroscience: the development of neurally inspired silicon-learning systems.
I have developed, in a standard CMOS process, a family of single-transistor devices that I call synapse transistors. Like neural synapses, synapse transistors provide nonvolatile analog memory, compute the product of this stored memory and the applied input, allow bidirectional memory updates, and simultaneously perform an analog computation and determine locally their own memory updates. I have fabricated a synaptic array that affords a high synapse-transistor density, mimics the low power consumption of nervous tissue, and performs both fast, parallel computation and slow, local adaptation. Like nervous tissue, my array simultaneously and in parallel performs an analog computation and updates the nonvolatile analog memory.
Although I do not believe that a single transistor can model the complex behavior of a neural synapse completely, my synapse transistors do implement a local learning function. I consider their development to be a first step toward achieving my goal of a silicon learning system.
https://resolver.caltech.edu/CaltechETD:etd-01092008-080326Retinomorphic vision systems : reverse engineering the vertebrate retina
https://resolver.caltech.edu/CaltechETD:etd-01092008-085128
Year: 1997
DOI: 10.7907/96W6-N605
This thesis seeks to explain how the retina satisfies both top-down constraints (functional) and the bottom-up constraints (structural) by analyzing simple physical models of the retina and mimicking its structure and function in silicon. In particular, I examine spatiotemporal filtering in the outer plexiform layer of the vertebrate retina, and show how outer retina processing is augmented by further processing in the inner plexiform layer, creating an efficient implementation that encodes moving stimuli efficiently over a wide range of speeds.
My working hypothesis is that biological sensory systems seek to optimize both functional and structural constraints. On the functional side, they must maximize information uptake from the environment while they minimize redundancy in their outputs. On the structural side, they must maximize resolving power in space and time, by making the processing elements small and fast, while they minimize wiring and energy consumption. If structure and function did indeed coevolve, as I assume, studying how structural and functional constraints are optimized simultaneously is our only hope of understanding why nature picks the solutions that we observe.
Addressing both structural and functional constraints requires combining science and engineering. Scientists study an existing structure, and seek to understand how it functions in an optimal or near-optimal fashion, based on theoretical grounds. Rarely does a scientist ask: Will the structure be more cost effective, more reliable, or more reproducible if a less-than-optimum function is chosen? Engineers, on the other hand, design an optimal implementation for some desired function, based on an existing set of standard primitives. Rarely does an engineer ask: Is this the most natural set of primitives to use for this particular function? Thus, neither discipline attempts to optimize both function and structure globally. In contrast, evolution, operating in a purely opportunistic fashion, continuously seeks increasingly elegant solutions that meet these constraints.
For these reasons, I have adopted a multidisciplinary engineering-science approach that combines analysis with synthesis. When tailored synergestically, this approach can shed light on questions about which neurobiologists care, while advancing the state of the art in sensory-system design.https://resolver.caltech.edu/CaltechETD:etd-01092008-085128Genetically Engineered Sensors of Cell Signaling
https://resolver.caltech.edu/CaltechTHESIS:04082013-160433360
Year: 2000
DOI: 10.7907/92c5-r851
<p>Measuring electrical activity in large numbers of cells with high spatial and temporal resolution is
a fundamental problem for the study of neural development and information processing. To address this
problem, we have constructed FlaSh: a novel, genetically-encoded probe that can be used to measure trans-membrane
voltage in single cells. We fused a modified green fluorescent protein (GFP) into a voltage-sensitive
potassium channel so that voltage dependent rearrangements in the potassium channel induce
changes in the fluorescence of GFP. A voltage sensor encoded into DNA has the advantage that it may be
introduced into an organism non-invasively and targeted to specific developmental stages, brain regions,
cell types, and sub-cellular compartments.</p>
<p>We also describe modifications to FlaSh that shift its color, kinetics, and dynamic range. We used
multiple green fluorescent proteins to produce variants of the FlaSh sensor that generate ratiometric signal
output via fluorescence resonance energy transfer (FRET). Finally, we describe initial work toward FlaSh
variants that are sensitive to G-protein coupled receptor (GPCR) activation. These sensors can be used to
design functional assays for receptor activation in living cells.</p>https://resolver.caltech.edu/CaltechTHESIS:04082013-160433360