CaltechAUTHORS: Combined
https://feeds.library.caltech.edu/people/Mead-C-A/combined.rss
A Caltech Library Repository Feedhttp://www.rssboard.org/rss-specificationpython-feedgenenMon, 14 Oct 2024 07:28:58 -0700Transistor AC and DC Amplifiers With High Input Impedance
https://resolver.caltech.edu/CaltechAUTHORS:20150901-113532040
Year: 1959
A class of transistor amplifiers is described in which high input impedance is achieved with bias stability comparable with that of ordinary low input impedance amplifiers. Input
impedances of several megohms shunted by one or two micromicrofarads are easily realized with simple circuits, and input resistances up to 100 megohms may be obtained with more elaborate circuitry. Other important properties are that input shunt capacitance can be
almost completely eliminated, the voltage gain is stabilized, and the output impedance is
low. Criteria for best noise performance are discussed. Typical practical measurements are
given, and various illustrative circuits are shown for both a-c and d-c amplifiershttps://resolver.caltech.edu/CaltechAUTHORS:20150901-113532040Transistor Switching Analysis
https://resolver.caltech.edu/CaltechAUTHORS:20161121-142936546
Year: 1960
With the widespread application of junction transistors in switching applications, the need
for a general method of analysis useful in the region of collector voltage saturation has become apparent.
Linear equivalent circuits using lumped elements have long been used for small signal calculations of
normally-biased transistors, but a comparable method for saturated transistors has been lacking. Recently,
Linvill [3] proposed the method of lumped models which allow the analysis of complex switching problems
with the ease of linear circuit calculations. The method is shown to be equivalent to a well-known linear
equivalent circuit under normal bias conditions. Examples of the application of the method and the use of
approximations are drawn from practical circuit problems. Emphasis is placed upon the understanding of
the physical phenomena involved, a necessary prerequisite to intelligent circuit design.https://resolver.caltech.edu/CaltechAUTHORS:20161121-142936546The Tunnel-Emission Amplifier
https://resolver.caltech.edu/CaltechAUTHORS:20150126-165741502
Year: 1960
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150126-165741502Relativity and the Scientific Method
https://resolver.caltech.edu/CaltechAUTHORS:20150831-161938603
Year: 1960
The recent PROCEEDINGS article by J. R. Pierce has triggered considerable adverse comment on Einstein's Theory of Relativity. In the maze of detail which was discussed, one very important principle was all but forgotten, i.e., the operation of the scientific method.https://resolver.caltech.edu/CaltechAUTHORS:20150831-161938603The operation of junction transistors at high currents and in saturation
https://resolver.caltech.edu/CaltechAUTHORS:20141217-151240614
Year: 1960
DOI: 10.1016/0038-1101(60)90009-5
The lumped-model characterization for junction transistors has been extended to current ranges where the transistor operation may no longer be considered linear. A number of effects are considered which contribute to the nonlinear behavior. In all cases it is shown that the self-bias cutoff effect plays an important part in the deterioration of performance at high currents.
In alloy transistors, both normally and inversely biased, an exact solution for the form of the current gain as a function of collector current is given for the case where the injected density is small compared with the equilibrium base majority-carrier density. This solution is shown to be applicable to normally biased diffused-base units. A decrease in current gain is predicted due to the self-bias effect. The sources of lateral base current are bulk recombination and injection into the emitter, the relative amount being immaterial since both are proportional to the injected density. In the small-area alloy devices, it is seen that the injected density becomes large compared with the base majority-carrier density before the transistor performance is appreciably degraded. In such cases the lateral base current is seen to be normally dominated by non-unity emitter efficiency.
In all cases, surface recombination is assumed to be the dominant source of total base current, and the first-order correction to the linear theory is shown to exhibit a 1/(1 + Ki_c) dependence. At higher currents all cases follow the observed 1/i_c proportionality.
The effect of nonlinear phenomena on saturation voltage is considered in some detail. The saturation voltage is shown to increase with drive current, again emphasizing the importance of avoiding large overdrive currents. The use of alloy transistors as low-level signal switches is discussed, indicating the necessity for high values of β and low values of K.https://resolver.caltech.edu/CaltechAUTHORS:20141217-151240614A Note on Tunnel Emission
https://resolver.caltech.edu/CaltechAUTHORS:20150831-162415263
Year: 1960
I would like to call attention to several errors in my recent communication.https://resolver.caltech.edu/CaltechAUTHORS:20150831-162415263Transistor switching analysis Part 1
https://resolver.caltech.edu/CaltechAUTHORS:20150128-161929182
Year: 1960
With the widespread application of junction transistors in switching applications, the need for a general method of analysis useful in the region of collector voltage saturation has become apparent. Linear equivalent circuits using lumped elements have long been used for small signal calculations of normally biased transistors, but a comparable method for saturated transistors has been lacking. Recently Linvill proposed the method of
lumped models which allow the analysis of complex switching problems with the case of linear circuit calculations. The method is shown to be equivalent to a well-known linear
equivalent circuit under normal bias conditions. Examples of the application of the method and the use of approximations are drawn from practical circuit problems. Emphasis is placed upon the understanding of the physical phenomena involved, a necessary prerequisite
to intelligent circuit design.https://resolver.caltech.edu/CaltechAUTHORS:20150128-161929182Transistor Switching Analysis Part 2
https://resolver.caltech.edu/CaltechAUTHORS:20150128-162326627
Year: 1960
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150128-162326627Transistor Switching Analysis Part 3
https://resolver.caltech.edu/CaltechAUTHORS:20150128-162613453
Year: 1960
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150128-162613453Tunneling Physics
https://resolver.caltech.edu/CaltechAUTHORS:20150227-164820030
Year: 1961
I should like to discuss what I feel to be the two fundamental principles in our understanding
of solid state physics to date. I think those of you who are experts on the subject will agree when I say that probably the outstanding features of solid state
physics, as opposed to other branches of physics, are (1) that we deal with systems having a periodic structure of atoms or molecules of some sort - a crystal lattice,
which is nearly perfect or nearly periodic over a large number of lattice spacings, and (2) that we deal with systems where the wave nature of the electron is of primary
importance. I should like to put these two ideas together by considering what would happen, on a one-dimensional model, if we try to propagate an electron wave down
through a periodic structure or lattice.https://resolver.caltech.edu/CaltechAUTHORS:20150227-164820030Operation of Tunnel‐Emission Devices
https://resolver.caltech.edu/CaltechAUTHORS:20141216-155808028
Year: 1961
DOI: 10.1063/1.1736064
The operation of a new class of devices employing the principle of tunnel emission is discussed. It is
shown that a controlled electron source may be obtained with the use of a metal-insulator-metal diode
structure where the second metal layer is very thin. A triode geometry may be secured by the addition of
an additional insulator and a metal collector layer. Limitations on the operating frequency, current density,
and current transfer ratio of such devices are discussed. Experimental results on diode and triode are discussed.
Experimental results on diode and triode structures which employ several materials are presented.
Successful triodes and vacuum emitters have been realized with the use of Al_2O_3, insulating films. Experiments
using Ta2_O_5 are described, and the results are discussed.https://resolver.caltech.edu/CaltechAUTHORS:20141216-155808028Anomalous capacitance of thin dielectric structures
https://resolver.caltech.edu/CaltechAUTHORS:MEAprl61
Year: 1961
DOI: 10.1103/PhysRevLett.6.545
The classical analysis of a plane parallel capacitor gives a capacitance which becomes infinite as the spacing between the metal electrodes approaches zero. The fact that real capacitors show a marked deviation from this behavior has not generally been recognized.(1,2) This communication describes experiments in which the deviations have been measured with some care.https://resolver.caltech.edu/CaltechAUTHORS:MEAprl61Transport of hot electrons in thin gold films
https://resolver.caltech.edu/CaltechAUTHORS:MEAprl62
Year: 1962
DOI: 10.1103/PhysRevLett.8.56
Considerable interest has been expressed of late concerning the transparency of thin metal films to electrons with energies of a few electron volts above the Fermi level.(1-4) In the present experiments, information concerning the mean free path for loss of energy in gold is determined directly from measurements of electron transport. The technique used is that of tunnel emission(3,4) in which electrons are caused to tunnel from a metal substrate through a thin insulating layer into a thin metal electrode through which a certain number pass into a vacuum where they are collected. Measurement of the relative number transmitted through the thin metal layer as a function of the thickness of the layer yields a direct measurement of the energy mean free path.https://resolver.caltech.edu/CaltechAUTHORS:MEAprl62Pulse Characteristic Display for Tunnel Emission Devices
https://resolver.caltech.edu/CaltechAUTHORS:20150901-114712753
Year: 1962
DOI: 10.1063/1.1717847
Recent studies on tunnel emission devices have
demonstrated that destruction normally occurs because
of high temperature generated within the thin film
structure while their electrical characteristics are being
measured. This difficulty has been overcome to a large
degree by pulse tests performed with the unit described
here. The most useful data to be observed on devices
designed to emit electrons into a vacuum are: (a) the voltampere characteristic of the diode (metal-insulator-metal structure), and (b) the transfer characteristic (i.e., emitted current vs diode current).https://resolver.caltech.edu/CaltechAUTHORS:20150901-114712753Electron transport mechanisms in thin insulating films
https://resolver.caltech.edu/CaltechAUTHORS:MEApr62
Year: 1962
DOI: 10.1103/PhysRev.128.2088
Tests have been performed on a number of Ta-Ta2O5-Au diodes of various thicknesses over a range of temperatures to determine the mechanism of current flow. The mechanism proposed for the current flow is field ionization of trap-type states at low temperatures and thermal ionization of these states at high temperatures and thermal ionization of these states at high temperature. High-temperature voltage-current data and low-temperature comparisons between forward and reverse characteristics agree well with the bulk-limited hypothesis and are in striking disagreement with barrier mechanisms. A discontinuity in the oxide properties is noted at a thickness of approximately 500 Å. High-temperature measurements at applied voltages less than the difference in the metal work functions yield an Ohmic characteristic with an activation energy of approximately 0.1 eV, consistent with an impurity conduction process but not with a barrier process.https://resolver.caltech.edu/CaltechAUTHORS:MEApr62Photoemission from Au and Cu into CdS
https://resolver.caltech.edu/CaltechAUTHORS:20141216-160600955
Year: 1963
DOI: 10.1063/1.1753781
Many metal-semiconductor surface barrier rectifiers
show photosensitivity for photon energies (hv) less than the semiconductor energy gap (E_g).
Cases in the literature include metals evaporated
or electrodeposited on elemental and III-V
compound semiconductor surfaces. In these studies
the source of the low-energy photocurrent, when
hv < E_g, was shown to be the photoemission of
carriers over the Schottky barrier between the metal
film and the semiconductor. An extensive investigation
has been reported for a series of metals,
particularly Cu and Au, electroplated on n-type CdS
with the conclusion that here also photoemission
from the metal is responsible for most of the low-energy photovoltage. However, recent studies have
questioned this conclusion for the CdS case. One
study proposed that the origin of the low-energy
photovoltaic response is electron photoexcitation
from Cu impurities located in the CdS and within a
diffusion length of the space charge region. Hole
conduction probably in the 3d Cu levels was postulated
for these samples, which had ≈ 30-ppm Cu. A second study interpreted the results as a p·n junction photovoltaic effect.https://resolver.caltech.edu/CaltechAUTHORS:20141216-160600955Metal contact double injection in GaAs
https://resolver.caltech.edu/CaltechAUTHORS:20150123-164938159
Year: 1963
DOI: 10.1109/PROC.1963.2355
Recent studies on the GaAs injection laser have indicated certain problems associated with the localization of the region of population inversion to the immediate vicinity of the p-n junction. It has also been pointed out that very heavy doping is necessary of laser action. However, in heavily doped material the absorption of light is large, raising the threshold current for laser action. These problems can be overcome simultaneously by using a metal-GaAs-metal structure operating in the double injection mode described by Lampert. A metal of low work function is used to inject electrons at one surface and one of high work function to inject holes at the opposite surface. When sufficient double injection occurs to neutralize the bulk between the electrodes, the voltage required to sustain the current drops to a low value.https://resolver.caltech.edu/CaltechAUTHORS:20150123-164938159Fermi Level Position at Semiconductor Surfaces
https://resolver.caltech.edu/CaltechAUTHORS:20150128-164226292
Year: 1963
DOI: 10.1103/PhysRevLett.10.471
There have been several recent reports of barrier height studies on metal-semiconductor interfaces. Metals of widely different work functions evaporated onto Si and GaAs surfaces indicated that in each case the energy difference
between the semiconductor conduction band edge
and Fermi level at the interface,φ_(Bn), was essentially
independent of the metal, which indicates
that the Fermi level is fixed by surface
states. In the present work barrier height measurements
have been made on a number of zinc-blende semiconductors to determine (a) if the barriers are in all cases determined by surface states, and (b) the relation between the Fermi
energy at the interface and the band gap E_g.https://resolver.caltech.edu/CaltechAUTHORS:20150128-164226292Barrier Height Studies on Metal-Semiconductor Systems
https://resolver.caltech.edu/CaltechAUTHORS:20141216-155213675
Year: 1963
DOI: 10.1063/1.1729121
Photovoltaic and space-charge capacitance measurements have been used to study the height of the Schottky barrier at the metal-semiconductor interface of a series of metals evaporated onto "vacuum cleaved" samples of n-type CdS and n- and p-type GaAs. Although the barrier heights for metal-CdS samples increase with increasing metal work function as predicted by simple theory, significant deviations were noted. The barrier heights measured on metal-GaAs samples at different temperatures show very little dependence on the metal and appear to be fixed relative to the valence band edge by surface states. The
results are compatible with the model in which the photoresponse, for photon energies less than the semiconductor energy gap, arises principally from photoemission of carriers from the metal into the semiconductor; however, the results are sensitive to the method of surface preparation and comparisons with other
work are difficult.https://resolver.caltech.edu/CaltechAUTHORS:20141216-155213675Conduction Band Minima in AlAs and AlSb
https://resolver.caltech.edu/CaltechAUTHORS:20150130-151553668
Year: 1963
DOI: 10.1103/PhysRevLett.11.358
The photoresponse of surface barrier rectifiers made by evaporating a metal such as gold or platinum on a cleaved surface of AlAs and AlSb has been measured in the front wall configuration. The photoresponse of such units for hv > E_g, where E_g is the energy gap, will be proportional to the absorption coefficient as long as the optical attenuation length is large compared to both the width
of the space-charge region and the minority carrier
diffusion length. The analysis is essentially
the same as that for p-n junctions with the exception
that the barrier is at the surface and hence
more sensitive to photons of high absorption coefficient.
Photoinjection of carriers from the metal into the semiconductor for photon energies where hv < E_g can also be observed.https://resolver.caltech.edu/CaltechAUTHORS:20150130-151553668Conduction Band Minima of Ga(As_(1−x)P_x)
https://resolver.caltech.edu/CaltechAUTHORS:20150128-102608367
Year: 1964
DOI: 10.1103/PhysRev.133.A872
Photoresponse of surface barriers on samples of Ga(As_(1−x_P_x) covering the range 0≤x≤1 has been measured. Thresholds corresponding to both direct and indirect band-to-band excitations within the semiconductor and also photoinjection from the metal have been identified. The threshold of the direct transition varies with composition from 1.37 eV in GaAs to 2.65 eV in GaP. The indirect transition was followed for x≳0.38 and again varied linearly from 2.2 eV in GaP to an extrapolated value in 1.62 eV in GaAs. The energy separation of the two conduction band minima in GaAs is in disagreement with previously reported values.https://resolver.caltech.edu/CaltechAUTHORS:20150128-102608367Conduction band minimum of CdTe
https://resolver.caltech.edu/CaltechAUTHORS:20141217-132959611
Year: 1964
DOI: 10.1016/0022-3697(64)90011-3
The spectral dependence of the photovoltaic effect for Au-n-type CdTe surface barrier cells is measured for photon energies near the CdTe intrinsic absorption edge at 298, 77, and 5°K. The results are viewed in terms of phonon assisted direct exciton absorption, phonon assisted exciton creation at a previously proposed lattice defect site, and indirect optical transitions. The data appears to favor the third mechanism although the second one is not ruled out as a possibility. The values for the direct transition energy gap obtained at the different temperatures compare favorably with those given by other work.https://resolver.caltech.edu/CaltechAUTHORS:20141217-132959611Fermi Level Position at Metal-Semiconductor Interfaces
https://resolver.caltech.edu/CaltechAUTHORS:20150128-111216077
Year: 1964
DOI: 10.1103/PhysRev.134.A713
The position of the Fermi level at a metal-semiconductor interface relative to the conduction band has been found to be a constant fraction of the semiconductor band gap for all but 3 of the 14 group IV or III-V semiconductors studied. In all cases, the position was essentially independent of the metal work function. This general result is not inconsistent with the limited theories of surface state energies now available. The three exceptional cases can be understood in terms of a first-order perturbation to the surface state energies correlated with a similar perturbation observed in the energy gap at the (111) zone edge. Experiments are also reported on Ga(As-P) alloys, and two II-VI materials showing distinctly different behavior.https://resolver.caltech.edu/CaltechAUTHORS:20150128-111216077Photothresholds in Mg_2Ge
https://resolver.caltech.edu/CaltechAUTHORS:20141216-154119053
Year: 1964
DOI: 10.1063/1.1702881
Optical absorption and surface barrier photoresponse measurements have been made on cleaved samples
of Mg_2Ge. The form of the results obtained from both techniques indicates an indirect transition at approximately
0.54 eV followed by a direct transition at approximately 1.8 eV.https://resolver.caltech.edu/CaltechAUTHORS:20141216-154119053Energy gap in sulphur
https://resolver.caltech.edu/CaltechAUTHORS:20141216-164458928
Year: 1964
DOI: 10.1016/0031-9163(64)90410-X
An excellent review of the electrical and optical
properties of α-sulphur has been given by
Moss. It is concluded that the conductivity is
intrinsic and that the energy gap is approximately
2.5 eV, corresponding to a thermal activation
energy of 1.3 eV. In this communication we present
evidence that the energy gap in α-sulphur is 3.8
eV, both electrons and hole being mobile, and that
the lower values previously reported are due to
excitation from defect states within the crystal.https://resolver.caltech.edu/CaltechAUTHORS:20141216-164458928Photoemissive Determination of Barrier Shape in Tunnel Junctions
https://resolver.caltech.edu/CaltechAUTHORS:20150130-152013585
Year: 1965
DOI: 10.1103/PhysRevLett.14.219
Tunnel junctions have been characterized
in terms of three parameters, the barrier
heights φ_1, and φ_2, and the width S, which generally
are determined by a fit of experimental
current-voltage characteristic curves with theory.
In metal-semiconductor systems barrier
heights have been determined independently
of other parameters from measurement of the
spectral dependence of photoresponse. We
wish to report the first results of the application
of this technique to the measurement of
the barrier heights in Al-Al_2O_3-A1 and Al-A1_20_3—Au tunnel junctions where the Al_2O_3 thickness
is in the range of 20 to 40 Å .https://resolver.caltech.edu/CaltechAUTHORS:20150130-152013585Electron Current Through Thin Mica Films
https://resolver.caltech.edu/CaltechAUTHORS:20150112-153251333
Year: 1965
Thin films of mica have unique attributes that are
exceptionally good for studies of high-field conduction
mechanisms in thin-film insulators and the
quantum mechanical tunneling of electrons from
metal to metal. The principal advantages of using
mica films are that the films are crystalline and
the cleavage planes occur every 10A. This property
results in films whose thicknesses are integral
multiples of lOÅ and whose surfaces are uniformly
parallel over sizable areas. Hence, very well-defined
metal-mica-metal strutures are possible.
Furthermore, the fact that the insulator is split
from a bulk sample allows the index of refraction,
dielectric constant, forbidden energy gap, and
trapping levels and their density to be obtained
directly from measurements performed on thick
samples of mica rather than requiring that these
properties be inferred from the conduction characteristics
alone. In the work to be described, all
the cleaving was done in a high vacuum just prior
to the evaporation of metal electrodes so as to avoid
air contamination at the interfaces. Results of
these studies indicate that the current through the
30 and 40Å films exhibited quantitative agreement
with the theoretical voltage and temperature dependence
derived by Stratton for the tunneling of
electrons directly from metal to metal. Thicker
films at room temperature exhibited volt-ampere
curves suggesting Schottky emission of electrons
from the cathode into the conduction band of mica.
However, the thermal activation energy was smaller
than that found from other measurements, and the
experimental Schottky dielectric constant was
larger than the square of the index of refraction.
These facts would indicate that the electrons were
being injected into polaron states in the insulator.
At low temperatures and high fields, the current
through the thicker films did not exhibit the Fowler-Nordheim dependence as would be predicted by a
simple extention of the theory of field emission into
a vacuum.https://resolver.caltech.edu/CaltechAUTHORS:20150112-153251333Surface States on Semiconductor Crystals; Barriers on the Cd(Se:S) System
https://resolver.caltech.edu/CaltechAUTHORS:20141216-161517797
Year: 1965
DOI: 10.1063/1.1754185
We report here measurements of surface barrier
heights of metal contacts on Cd(Se:S) crystals in
which a continuous transition is observed between
the CdS case in which the barrier height varies as
the metal work function to the CdSe case where the
barrier height is essentially independent of the metal.
The results have fundamental implications concerning
the nature of the surface states and their
relationship to the properties of the semiconductor.https://resolver.caltech.edu/CaltechAUTHORS:20141216-161517797Electrical Transport and Contact Properties of Low Resistivity n Type Zinc Sulfide Crystals
https://resolver.caltech.edu/CaltechAUTHORS:20141216-162020351
Year: 1965
DOI: 10.1063/1.1754243
This Letter describes some electrical contact and
transport properties of ZnS single crystals having
room-temperature resistivities in the range of 1 to
10 ohm-cm. Previous electrical transport measurements
on ZnS have been done mainly at high temperatures
or under photoexcitation. Electrical
contacts to ZnS which display ohmic characteristics
at room temperature have been described by Alfrey
and Cooke. A serious limitation to a more extensive
investigation of the electrical properties of ZnS
has been the difficulty in providing ZnS crystals
with contacts which would stay ohmic at low temperatures.
It has also been difficult to dope ZnS
n-type without simultaneously introducing large
concentrations of native acceptor defects.https://resolver.caltech.edu/CaltechAUTHORS:20141216-162020351Electronic Processes in α-Sulfur
https://resolver.caltech.edu/CaltechAUTHORS:20141217-135230195
Year: 1965
DOI: 10.1016/0022-3697(65)90047-8
The mobilities of photo-generated electrons and holes in orthorhombic sulfur are determined by drift mobility techniques. At room temperature electron mobilities between 0.4 cm^2/V-sec and 4.8 xm^2/V-sec and hole mobilities of about 5.0 cm^2/V-sec are reported. The temperature dependence of the electron mobility is attributed to a level of traps whose effective depth is about 0.12 eV. This value is further supported by both the voltage dependence of the space-charge-limited, d.c. photocurrents and the photocurrent versus photon energy measurements.
As the field is increased from 10kV/cm to 30kV/cm a second mechanism for electron transport becomes appreciable and eventually dominates. Evidence that this is due to impurity band conduction at an appreciably lower mobility (4.10^(-4) cm^2/V-sec) is presented. No low mobility hole current could be detected for fields below 35 KV/cm. When fields exceeding 30 kV/cm for electron transport and 35 kV/cm for hole transport are applied, avalanche phenomena are observed. The results obtained are consistent with recent energy gap studies in sulfur.
The theory of the transport of photo-generated carriers is modified to include the case of appreciable thermo-regeneration from the traps in one transit time.https://resolver.caltech.edu/CaltechAUTHORS:20141217-135230195Surface barriers on ZnSe and ZnO
https://resolver.caltech.edu/CaltechAUTHORS:20141217-150924242
Year: 1965
DOI: 10.1016/0031-9163(65)90295-7
We report measurements of surface barrier heights of several metals on vacuum cleaved ZnSe and ZnO surfaces, indicating that both of these materials behave as expected for materials without surface states. Samples were prepared by cleavage in a vacuum in the stream of evaporating metal, thus insuring a clean interface. Barrier heights were measured using the photoresponse technique on the ZnSe and for the higher barriers on the ZnO, and by analysis of the [-V characteristic for the lower barriers on ZnO (Cu, In, Al, Ti). The detailed procedure has been described previously [1]. The results of this study are shown in fig. 1, together with the values for ZnS taken from Aven and Mead [2]. The probable errors are greater for the lower barriers, in some cases it being only possible to give an upper limit (as indicated by the bars). For the higher barriers the probable error is less than 0.1 eV.https://resolver.caltech.edu/CaltechAUTHORS:20141217-150924242Metal-semiconductor surface barriers
https://resolver.caltech.edu/CaltechAUTHORS:20141217-151530128
Year: 1966
DOI: 10.1016/0038-1101(66)90126-2
The physical principles underlying the metal-semiconductor barrier are discussed in the light of recent experimental results. A semi-empirical approach for predicting the type of contact to be expected at an arbitrary metal-semiconductor interface is presented.https://resolver.caltech.edu/CaltechAUTHORS:20141217-151530128Electron Transport in Thin Insulating Films
https://resolver.caltech.edu/CaltechAUTHORS:20150902-160503489
Year: 1966
Experiments on the electron transport through thin insulating barriers have been performed with
diodes of Ta-Ta_2O_5-Au, Ta-Ta_2O_5-Al, Ta-Ta_2O_5-Bi, Zn-ZnO-Au, Al-Al_2O_3-Al and Al-Al_2O_3-Au.
The analysis of the dependence of current on temperature and film thickness allows a distinction
of two cases: imperfect and perfect dielectrics. In the former case the mechanism for electron
transport is field ionisation of trap-type states at low temperatures and thermal ionisation of this
states at higher temperatures. In the latter case Schottky-Emission and field emission have been
observed.https://resolver.caltech.edu/CaltechAUTHORS:20150902-160503489Schottky Barrier Gate Field Effect Transistor
https://resolver.caltech.edu/CaltechAUTHORS:20150123-165629708
Year: 1966
DOI: 10.1109/PROC.1966.4661
An obvious addition to the ever-growing family of field-effect devices is a field-effect transistor with a Schottky barrier gate. It is the purpose of this correspondence 1) to demonstrate that indeed such a device does function as expected and 2) to point out several advantages of such a structure under certain circumstances. A schematic cross section of the device is shown in Fig. 1. The gate consists of a metal in intimate contact with the clean semiconductor surface. Clearly the ohmic contacts can be placed either on top of or under the semiconductor layer.https://resolver.caltech.edu/CaltechAUTHORS:20150123-165629708Voltage Dependence of Barrier Height in AIN Tunnel Junctions
https://resolver.caltech.edu/CaltechAUTHORS:20141216-162848152
Year: 1966
DOI: 10.1063/1.1754505
We report measurements of barrier heights on
AI-AIN-Mg thin-film structures as a function of
applied voltage and insulator thickness. These results
are in disagreement with currently accepted
theories based upon image potential and/or field
penetration of the electrodes.https://resolver.caltech.edu/CaltechAUTHORS:20141216-162848152Surface Barriers on SnO_2
https://resolver.caltech.edu/CaltechAUTHORS:20150831-170804728
Year: 1966
DOI: 10.1016/0031-9163(66)90742-6
We report measurements made on Schottkey type surface barriers between evaporated metal layers and n-type SnO_2 crystals of approximately 0.2Ω cm resistivity.https://resolver.caltech.edu/CaltechAUTHORS:20150831-170804728Semiconductors as Electrooptic Modulators for Infrared Radiation
https://resolver.caltech.edu/CaltechAUTHORS:20140226-151844706
Year: 1966
DOI: 10.1109/JQE.1966.1073840
The electrooptic properties of a number of
semiconductors were investigated. We were
particularly interested in the possibility of
using these materials for modulation of
infrared radiation (λ > 3µ), since many of
the efficient modulation materials for the
shorter wavelengths, such as KTN and
KDP, are opaque in this region.https://resolver.caltech.edu/CaltechAUTHORS:20140226-151844706Dielectric constants and infrared absorption of GaSe
https://resolver.caltech.edu/CaltechAUTHORS:20141217-144018278
Year: 1966
DOI: 10.1016/0022-3697(66)90258-7
Capacitance measurements on thin, fully depleted GaSe samples indicate a low frequency dielectric constant ϵ_0 = 8.0 ± 0.3 for E||c. Infrared reflectivity measurements show a single resonance for each polarization of the electric vector. Dispersion analysis gives ϵ_∞ = 7.1 and ϵ_0 = 7.6 for E||c and ϵ_∞ = 8.4 and ϵ_0 = 10.2 for E⊥c. More accurate channel spectra give ϵ_∞ = 7.45 and ϵ_0 = 9.80 for E⊥c. A number of weak two phonon combination bands are observed.https://resolver.caltech.edu/CaltechAUTHORS:20141217-144018278Experimental Determination of E−k Relationship in Electron Tunneling
https://resolver.caltech.edu/CaltechAUTHORS:20150130-152604952
Year: 1966
DOI: 10.1103/PhysRevLett.16.939
We report here measurements of electron
tunneling through thin AlN films in which the
imaginary component of the propagation vector
in the forbidden band has been determined as
a function of energy from the dependence of
the tunneling current upon insulator thickness.
The relationship so derived agrees well with
Franz's empirical relationship for a material
with the 4.2-eV forbidden-band energy of AlN.
These results allow the prediction of voltage-current
characteristics over the entire range
of experimental variables with no arbitrary
adjustable parameters, and also subject to several
internal self-consistency checks. In each
case complete consistency is observed, To
the authors' knowledge, this represents the
first unambiguous demonstration of such consistency
in thin-film tunneling.https://resolver.caltech.edu/CaltechAUTHORS:20150130-152604952Barrier Lowering and Field Penetration at Metal-Dielectric Interfaces
https://resolver.caltech.edu/CaltechAUTHORS:20141216-163126917
Year: 1966
DOI: 10.1063/1.1754598
We report here photoemission measurements on
Si-SiO_2-Al structures in which the metal-SiO_2
barrier energy has been determined as a function
of the electric field strength E in the dielectric. The
expected barrier lowering is the sum of two terms:
a) the Schottky term, proportional to E^(1/2) and b)
a term due to the penetration of the electric field
into the metal electrode, proportional to E. The
experimental results are in good agreement with
the model, where the Schottky effect involves the
optical value of the dielectric constant of the oxide
and the Thomas-Fermi screening distance in the
metal is 1 Å. To our knowledge this represents the
first unambiguous quantitative determination of either effect in a polar dielectric, although the
Schottky effect alone has been observed in silicon.https://resolver.caltech.edu/CaltechAUTHORS:20141216-1631269175C3 - GaAs as an electrooptic modulator at 10.6 microns
https://resolver.caltech.edu/CaltechAUTHORS:20150114-105353734
Year: 1966
DOI: 10.1109/JQE.1966.1074037
The electrooptic properties of a number of semi-conductors were investigated. Of particular interest was the possibility of using these materials for modulation o infrared radiation, since many of the efficient modulation materials for the shorter wavelengths, such as KTN and KDP, are opaque in this region. We have investigated experimentally the modulation potential of a number of semiconducting materials. These include ZnS and GaAs of the noncentrosymmetric 43m class. The electrooptic coefficients were determined by using a CO_2, 10.6μ and a He-Ne 3.39 μ laser as the radiation source. Based on our experiments, GaAs appears as a suitable material for infrared modulation at λ > 10μ.https://resolver.caltech.edu/CaltechAUTHORS:20150114-105353734The effect of nonparabolic energy bands on tunneling through thin insulating films
https://resolver.caltech.edu/CaltechAUTHORS:20141217-143747442
Year: 1966
DOI: 10.1016/0022-3697(66)90238-1
Previously derived equations for the volt-current characteristic are applied to trapezoidal barriers, keeping the energy momentum relations arbitrary. Techniques for deriving the energy-momentum relation in the forbidden gap of the insulating film are presented.https://resolver.caltech.edu/CaltechAUTHORS:20141217-143747442Barrier energies in metal-silicon dioxide-silicon structures
https://resolver.caltech.edu/CaltechAUTHORS:20141217-141254267
Year: 1966
DOI: 10.1016/0022-3697(66)90118-1
Metal-silicon dioxide barrier energies have been determined for six metals, Ag, Al, Au, Cu, Mg and Ni, deposited on thermally oxidized silicon. Results obtained by two different measurement methods, the photoemission technique and the MOS capacitance-voltage technique, are in excellent agreement with one another. Values of the barrier energy ϕ_M range from 2.3 eV for Mg to 4.2 eV for Ag and are roughly proportional to the electronegativities of the metals. The siliconsilicon dioxide barrier energy (measured from the silicon valence band) has also been determined and was found to be 4.35 eV independent of silicon orientation or type.https://resolver.caltech.edu/CaltechAUTHORS:20141217-141254267The Tunneling Time of an Electron
https://resolver.caltech.edu/CaltechAUTHORS:20141216-154636409
Year: 1967
DOI: 10.1063/1.1709888
There is a widely spread misconception regarding the physical significance of the various tunneling times currently used to describe metal-insulator-metal tunneling phenomena. Using quantum mechanics, the transition time of an electron tunneling from a state on one side of the barrier to a state on the other side can be determined. This time is the period of interaction between the
electron and the barrier, since before and after the transition, the electron is in a quantum state of one of the metals. Furthermore, the RC time constant of the sandwich-like device and the electron transition or interaction time are equivalent representations
of the same physical parameter. But none of these times is the quasiclassical "transmission time" analyzed by Hartman, which has become widely accepted as the electron-barrier interaction time, although this was clearly not his intention. In this communication we wish to point out that it is the (quantum mechanical) transition time which is the characteristic time of tunneling phenomena.https://resolver.caltech.edu/CaltechAUTHORS:20141216-154636409Conduction through TiO_2 thin films with large ionic space charge
https://resolver.caltech.edu/CaltechAUTHORS:20141217-145426453
Year: 1967
DOI: 10.1016/0022-3697(67)90175-8
The electrical properties are described for thin film sandwiches of Al-TiO_2-Al with
films varying in thickness from 100 to 410 Å. The results are interpreted in terms of a large ionic
space charge in the TiO_2 films. By selecting a sample of appropriate thickness, it was possible to make a detailed comparison of the. experimental results with the theory of the preceding paper. Using the barrier energies at the two electrodes determined independently from photoelectric
measurements and adjusting a single parameter, the characteristic temperature T_0 to the results,
we obtain good agreement for the dependence of both current and capacitance on voltage and temperature. From the value of T_0 so determined we calculate a maximum ionic space-charge density adjacent to the electrode interfaces of approximately 5 mole per cent which conforms with
typical values of saturation concentrations of impurities quoted for TiO_2. The dependence of conductance and capacitance on frequency is also considered and shown to be in qualitative agreement with the theoretical model.https://resolver.caltech.edu/CaltechAUTHORS:20141217-145426453Electric field dependence of GaAs Schottky barriers
https://resolver.caltech.edu/CaltechAUTHORS:20141217-151846023
Year: 1968
DOI: 10.1016/0038-1101(68)90079-8
The bias dependence of the photoelectric barrier energy of n-GaAs-Al diodes has been measured. The devices were fabricated by cleavage of the GaAs in an evaporating stream of metal in a vacuum of 10^(−8) torr. The barrier energies at various bias levels were determined by extrapolation of the photoresponse vs. photon energy plots. The electric field dependence of the photoresponse was also measured at constant photon energy. The calculated change in barrier energy from the latter method was then compared with the changes in extrapolated values of barrier energy. A small systematic disagreement was observed and attributed to the effects of collection efficiency in the GaAs. The field dependence of Schottky barriers on 5×10^(16) GaAs was found to be in good agreement with that expected from the exponential charge distribution associated with the surface states which determine the barrier energy.https://resolver.caltech.edu/CaltechAUTHORS:20141217-151846023Currents through thin films of aluminum nitride
https://resolver.caltech.edu/CaltechAUTHORS:20141217-150418676
Year: 1968
DOI: 10.1016/0022-3697(68)90218-7
The current-voltage characteristics of thin film structures consisting of two metal electrodes separated by a thin insulating layer of AlN were measured as a function of insulator thickness. In thinner structures, the dependence of the current on voltage and insulator thickness was that expected from direct electron tunneling through a trapezoidal barrier. The characteristics were used to determine the barrier energies at the metal insulator interfaces and the energy-momentum relationship over a considerable portion of the AlN forbidden energy gap. In structures with thicker insulating regions, temperature-independent currents were observed which because of their dependence on voltage and insulator thickness could not be attributed to direct electron tunneling.https://resolver.caltech.edu/CaltechAUTHORS:20141217-150418676Electrical conduction through thin amorphous SiC films
https://resolver.caltech.edu/CaltechAUTHORS:20150901-120328599
Year: 1968
DOI: 10.1016/0040-6090(68)90014-X
The current density through amorphous SiC films 80 to 800 Å thick deposited pyrolytically on refractory metal substrates is described by j = K(T,d)V^nn(T,d) where T is the absolute temperature and d the film thickness. This type of electrical characteristic is similar to that obtained for compressed granulated SiC pellets or varistors and also for amorphous thin films of semiconductors and insulators.https://resolver.caltech.edu/CaltechAUTHORS:20150901-120328599Energy-Momentum Relationship in InAs
https://resolver.caltech.edu/CaltechAUTHORS:20150130-153034191
Year: 1968
DOI: 10.1103/PhysRevLett.21.605
We have performed surface-barrier tunneling measurements on p-type InAs and found the energy dependence of the wave vector in the forbidden gap to be in agreement with Franz's relationship based on a two-band model.https://resolver.caltech.edu/CaltechAUTHORS:20150130-153034191GaSe Schottky barrier gate FET
https://resolver.caltech.edu/CaltechAUTHORS:20150126-163615311
Year: 1968
DOI: 10.1109/PROC.1968.6658
Advantages of the Schottky barrier gate technique are reviewed, and an experimental field-effect transistor constructed from p-type GaSe is discussed. Device characteristics are consistent with calculations based on material parameters and the geometry employed.https://resolver.caltech.edu/CaltechAUTHORS:20150126-163615311Surface barriers on layer semiconductors: GaSe
https://resolver.caltech.edu/CaltechAUTHORS:20141217-150028682
Year: 1968
DOI: 10.1016/0022-3697(68)90170-4
Metallic surface barriers formed on the layer compound GaSe are studied by the photoresponse technique. The dependence of barrier potential vs. etectronegativity of the deposited metal is found to be linear with slope ≅ 0.6.https://resolver.caltech.edu/CaltechAUTHORS:20141217-150028682The Presence of Deep Levels in Ion Implanted Junctions
https://resolver.caltech.edu/CaltechAUTHORS:20141215-165827280
Year: 1968
DOI: 10.1063/1.1652619
It has been found that ion implantation doping results in the generation and diffusion of defect species, forming deep trapping levels. The effect of these levels on the electrical characteristics of zinc‐implanted GaAs diodes has been observed for the case of 70‐kV implantation at 400°C into substrates with n‐type concentrations ranging from 1 × 10^16 to 1.8 × 10^18 atoms/cm^3. Capacitance‐voltage measurements have indicated the presence of a semi‐insulating layer in the diodes, varying in thickness from 0.18 μ for the most heavily doped substrate to 2.7 μ for the lightest. Frequency dependence of the junction capacitance and power law variation of forward current vs voltage have also been observed and are attributed to deep levels.https://resolver.caltech.edu/CaltechAUTHORS:20141215-165827280Some Properties of Exponentially Damped Wave Functions
https://resolver.caltech.edu/CaltechAUTHORS:20150223-145247878
Year: 1969
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150223-145247878Physics of Interfaces
https://resolver.caltech.edu/CaltechAUTHORS:20150223-144739659
Year: 1969
It has long been known that when a metal is placed in contact with a semiconductor a rectifying contact often results. This rectification is a result
of an energy barrier between the metal and the semiconductor. In order to form a nonrectifying or ohmic contact, two general approaches can be applied: either (1) the barrier energy can be reduced to a low
enough value that the thermally excited current over the barrier is large enough for the application involved or (2) the semiconductor can be doped to a high carrier density to allow quantum mechanical tunneling to take
place. The physical principles of these processes are discussed in this article.https://resolver.caltech.edu/CaltechAUTHORS:20150223-144739659The Effect of Trapping States on Tunneling in Metal Semiconductor Junctions
https://resolver.caltech.edu/CaltechAUTHORS:20141216-150229434
Year: 1969
DOI: 10.1063/1.1652641
The tunneling behavior of Schottky barriers has been investigated by several authors. The I-V characteristics exhibit an exponential form in the forward direction which can be used to determine the energy vs complex momentum dispersion relation for charge carriers in the forbidden
gap. In this paper we show that under proper conditions the presence of traps can increase the tunneling probability and result in a reduction in the slope of the log I vs V characteristic by a factor of 2.https://resolver.caltech.edu/CaltechAUTHORS:20141216-150229434Schottky Barriers on GaAs
https://resolver.caltech.edu/CaltechAUTHORS:20150901-161853962
Year: 1969
DOI: 10.1103/PhysRev.177.1164
The forward current of Schottky barriers on n-type GaAs is investigated as a function of electron concentration in the range of 8×10^17 to 8×10^18 cm^−3 at temperatures 297-4.2°K. Both vacuum-cleaved and chemically polished surfaces are used. The majority of the junctions studied are gold Schottky barriers, but tin and lead contacts are also examined. The predominant current mechanism is field emission at liquid-nitrogen temperature and below for the range of electron concentrations used. These data are in excellent quantitative agreement at 77°K with the field-emission analysis of Padovani and Stratton if one uses a two-band model for the imaginary wave number kn. At 297°K, thermionic field emission predominates, but for an electron density above 3×1018 cm−3 the field-emission mechanism with a two-band model still gives reasonable agreement.https://resolver.caltech.edu/CaltechAUTHORS:20150901-161853962Fundamental transition in the electronic nature of solids
https://resolver.caltech.edu/CaltechAUTHORS:KURprl69
Year: 1969
DOI: 10.1103/PhysRevLett.22.1433
Striking evidence for a fundamental covalent-ionic transition in the electronic nature of solids is presented.https://resolver.caltech.edu/CaltechAUTHORS:KURprl69Origin of Field Dependent Collection Efficiency In Contact Limited Devices
https://resolver.caltech.edu/CaltechAUTHORS:20151008-165307664
Year: 1969
It has been established that diffusion of photo-generated carriers into the electrode
can be an important limitation of the collection efficiency of surface barrier limited
photo conductors. The relevance of these results to devices is discussed with
emphasis on particle detectors.https://resolver.caltech.edu/CaltechAUTHORS:20151008-165307664Origin of Field-Dependent Collection Efficiency in Contact-Limited Photoconductors
https://resolver.caltech.edu/CaltechAUTHORS:20141216-150707692
Year: 1969
DOI: 10.1063/1.1652824
It has been established that diffusion of photogenerated carriers into the electrode can be an important limitation of the collection efficiency of surface-barrier-limited photoconductors.https://resolver.caltech.edu/CaltechAUTHORS:20141216-150707692Surface barriers on layer semiconductors: GaS, GaSe, GaTe
https://resolver.caltech.edu/CaltechAUTHORS:20150309-153629367
Year: 1969
DOI: 10.1016/0022-3697(69)90179-6
Surface barriers formed on the gallium-chalcogenide layer semiconductors GaS, GaSe and GaTe are studied by the photoresponse technique. The observed behavior is qualitatively similar to that of non-layer compounds.https://resolver.caltech.edu/CaltechAUTHORS:20150309-153629367Tunneling in CdTe Schottky Barriers
https://resolver.caltech.edu/CaltechAUTHORS:20150901-163217733
Year: 1969
DOI: 10.1103/PhysRev.184.780
The tunneling characteristics of metal contacts on n−CdTe have been measured. Both the forward- and reverse-bias characteristics are in good agreement with the two-band model for the energy-complex-momentum relationship. The presence of trapping states increased the magnitude of the tunneling current at low levels by providing a two-step transition. The slope of the forward-bias log_e J−versus−V curves for tunneling through the intermediate states was reduced by a factor of 2.https://resolver.caltech.edu/CaltechAUTHORS:20150901-163217733Characteristics of Aluminum-silicon Schottky Barrier Diode
https://resolver.caltech.edu/CaltechAUTHORS:20150929-092612724
Year: 1970
DOI: 10.1016/0038-1101(70)90039-0
Aluminumn-type silicon Schottky barrier diodes with near-ideal characteristics have recently been developed. In this paper the characteristics of such a Schottky barrier are discussed. The I–V characteristics agree well with the theoretical thermionic emission model. The barrier height is determined from the saturation current, temperature dependence of forward current, and photoemission to be0.69±0.01eV. The switching measurements show no minority carrier storage, as expected. The low-frequency noise is very low and is comparable to the best p-n junction and guard-ring Schottky barrier. These desirable features, coupled with the simple process of the Al-nSi Schottky barrier, make them attractive in a variety of applications.https://resolver.caltech.edu/CaltechAUTHORS:20150929-092612724Influence of carrier diffusion effects on window thickness of semiconductor detectors
https://resolver.caltech.edu/CaltechAUTHORS:20151007-161136079
Year: 1970
DOI: 10.1016/0029-554X(70)90159-X
Carrier diffusion effects within the depletion region can have a large influence in determining the window thickness x_w of surface barrier detectors. If the surface is assumed to be a perfect sink, carrier diffusion (against the drift field) to the surface leads to x_w ≈ kT/qE where E is the field at the surface. Calculated values of x_w are in reasonable agreement with previously published values of window thicknesses. Surface preparation techniques can influence the amount of charge lost, as can
plasma erosion times.https://resolver.caltech.edu/CaltechAUTHORS:20151007-161136079"Polywater": A Hydrosol?
https://resolver.caltech.edu/CaltechAUTHORS:20150219-113338016
Year: 1970
DOI: 10.1126/science.167.3926.1720
Measurements of the dielectric constant and the effective parallel conductance of a specimen of anomalous water suggest that anomalous water is a hydrosol consisting of finely divided particulate matter suspended in ordinary water. Scanning electron micrography confirms the presence of particulate matter. These new experimental data provide an alternative explanation for the properties of anomalous water.https://resolver.caltech.edu/CaltechAUTHORS:20150219-113338016Charge transport through α-monoclinic selenium
https://resolver.caltech.edu/CaltechAUTHORS:20150929-092047338
Year: 1970
DOI: 10.1016/0022-3697(70)90309-4
The existence of surface barriers on α-monoclinic selenium crystals has been demonstrated. Photometric measurements indicate electron barrier energies of 1.05 and 1.3 eV, respectively, for Ga and Au contacts. The mobilities of holes and electrons have been measured by a time-of-flight technique to be about 0.2cm^2/Vsec and 1.6cm^2/Vsec, respectively, at room temperature. The hole mobility was found to be limited by traps 0·23 ± 0.01 eV above the valence levels, while the electron mobility is an intrinsic mobility limited by scattering. It was found that in the region of low carrier density (i.e. no space charge effects) the collection efficiency was limited by diffusion of carriers into the metal contact.https://resolver.caltech.edu/CaltechAUTHORS:20150929-092047338Physical model for burst noise in semiconductor devices
https://resolver.caltech.edu/CaltechAUTHORS:20150212-155102555
Year: 1970
DOI: 10.1016/0038-1101(70)90102-4
A physical model for burst noise in p−n junction devices is presented. It is proposed that burst noise results when the current through a defect is modulated by a change in the charge state of a single recombination-generation center located adjacent to the defect. The burst noise amplitude and pulse widths are related to the basic properties of the recombination-generation center and the defect. The model leads to a simple interpretation of the equivalent circuit for diodes which exhibit this type of noise.https://resolver.caltech.edu/CaltechAUTHORS:20150212-155102555Surface Barriers on Zinc Oxide
https://resolver.caltech.edu/CaltechAUTHORS:20141216-151406070
Year: 1970
DOI: 10.1063/1.1659509
The surface barrier systems consisting of gold and palladium on chemically prepared zinc oxide have
been investigated in detail. Surface barrier energies have been determined by photoresponse, forward
current versus voltage, thermal activation energy, and capacitance-voltage methods. Agreement in barrier
energies obtained by the four methods is excellent. The barrier energy for gold is 0.66 eV and for palladium
is 0.60 eV. Forward current-voltage characteristics were in quantitative agreement with simple Bethe
diode theory as modified by the presence of image force lowering. The reverse current-voltage characteristic
is in quantitative agreement with that expected from the simple image force lowering of the barrier, over
a bias range of from 0.1 to 3 V. Carrier concentration derived from resistivity and Hall measurements
agreed with that obtained from capacitance-voltage measurements. We believe this represents the first
comprehensive study where such quantitative consistency has been demonstrated on a compound semiconductor
barrier system. Existence of a deep level trap is indicated via the effects on capacitance measurements.https://resolver.caltech.edu/CaltechAUTHORS:20141216-151406070Contact-limited currents in metal-insulator-metal structures
https://resolver.caltech.edu/CaltechAUTHORS:MCGjap70b
Year: 1970
DOI: 10.1063/1.1659514
The physical mechanisms underlying current flow in solid-state MIM structures are reviewed with emphasis on criteria for determining the dominant conduction mechanism in a given experimental situation. Measurements of the bias and temperature dependence of currents through structures incorporating a thin film of single-crystal gallium selenide are reported, and are shown to be in excellent agreement with the predictions of a simple physical model of contact-limited emission. Independently measured properties of bulk single-crystal gallium selenide are used in all calculations; no adjustable parameters are employed. We believe that this study presents unequivocal evidence for contact-limited thermionic currents in solid-state MIM structures.https://resolver.caltech.edu/CaltechAUTHORS:MCGjap70bTunneling Currents and the E-k Relation
https://resolver.caltech.edu/CaltechAUTHORS:KURprl70
Year: 1970
DOI: 10.1103/PhysRevLett.25.756
The energy-momentum dispersion relation within the forbidden gap of a single-crystal insulator (in this case, GaSe) has been accurately determined using a simple physical model to describe tunneling currents in appropriate thin-film structures. This dispersion relation, calculated from experimental current-voltage data, is shown to be intrinsic to GaSe and capable of quantitatively predicting tunneling currents. The work reported here represents the first quantitative calculation of tunneling currents in metal-insulator-metal structures with all parameters relevant to the experiment independently determined.https://resolver.caltech.edu/CaltechAUTHORS:KURprl70Electrical Characteristics of Sphingomyelin Bilayer Membranes
https://resolver.caltech.edu/CaltechAUTHORS:20150212-155536034
Year: 1970
DOI: 10.1016/S0006-3495(70)86354-8
Current-voltage characteristics and the conductivity temperature dependence of sphingomyelin bilayer membranes have been determined. The resistances were of the order of 10^8 Ω-cm^2 and exhibited ohmic behavior up to approximately 25 mv followed by increasing conductivity with applied voltage. The current is found to be proportional to a hyperbolic sine function of the voltage. The temperature dependence indicates a thermally activated conduction mechanism. The observed behavior closely follows a kinetic model involving a barrier modified by the applied electric field, the rate-limiting process being the surmounting of the barrier by the impinging ions. The model allows predictions to be made over a wide range of conditions.https://resolver.caltech.edu/CaltechAUTHORS:20150212-155536034Tunneling Currents in Zinc Oxide
https://resolver.caltech.edu/CaltechAUTHORS:20141216-151026878
Year: 1970
DOI: 10.1063/1.1658664
An examination of the current-voltage characteristics of gold and palladium surface barriers on degenerate
zinc oxide has been made. Both chemically prepared and cleaved surfaces were studied. The current conduction
mode is shown to be thermionic-field emission at room temperature and to be pure field emission at
liquid-nitrogen temperatures. The voltage dependence of the current is in good agreement with theory.
The observed current magnitudes in both current modes were approximately one-tenth that calculated
by simple theory.https://resolver.caltech.edu/CaltechAUTHORS:20141216-151026878Current Flow through Thin Insulating Films: Basic Principles and Device Applications
https://resolver.caltech.edu/CaltechAUTHORS:20141215-165521589
Year: 1971
DOI: 10.1116/1.1316370
The fundamental physics underlying current flow through thin insulating films is reviewed, with emphasis placed on those experiments central to the identification of the dominant current flow mechanism in a given structure. Recent data obtained on metal-insulator-metal structures incorporating single crystal thin films represents unambiguous observation of both thermionic emission and tunneling. Device applications of thin films are also summarized.https://resolver.caltech.edu/CaltechAUTHORS:20141215-165521589Direct interelectrode tunneling in GaSe
https://resolver.caltech.edu/CaltechAUTHORS:KURprb71
Year: 1971
DOI: 10.1103/PhysRevB.3.3368
Using thin films of the layer compound gallium selenide, we have fabricated experimental structures which are nearly ideal for the study of tunneling currents. All of the parameters relevant to current flow in these structures can be independently determined since single-crystal gallium selenide films have the properties of the bulk material and also well-defined interfaces. A new analytical technique for determining the energy-momentum dispersion relation within the forbidden gap of a solid is discussed and applied to current-voltage data obtained from metal-GaSe-metal structures. The resulting E-k relation is shown to be an intrinsic property of GaSe. Tunneling currents in GaSe are shown to be quantitatively understood in terms of this E-k relation, the geometry of a given structure, and a simple model of current flow via tunneling.https://resolver.caltech.edu/CaltechAUTHORS:KURprb71Zero-bias Contact Resistances of Au-GaAs Scottky Barriers
https://resolver.caltech.edu/CaltechAUTHORS:20150929-091638824
Year: 1971
DOI: 10.1016/0038-1101(71)90147-X
The contact resistances of gold-GaAs Schottky barriers have been measured at liquid nitrogen temperatures over the range of electron concentrations between 3.2 × 10^(18) to 2.4 × 10^(19) cm^(−3). Our theoretical treatment is based on that of Padovani and Stratton but modified to include Franz's two-band model for the imaginary wave vector of the tunneling electrons and Conley and Mahan's correction to the space-charge potential in degenerate semiconductors. The results correlate well with the theory in the 3.2 × 10^(18) to 5.6 × 10^(18) cm^(−3) range of concentrations. The theory must be extended to include the effects of fluctuating depletion width (a suggestion originally made by Bethe) to adequately explain the low contact resistances observed with the heaviest doped GaAs. This material is a degenerate and heavily compensated tin-alloy regrowth commonly used as an ohmic contact.https://resolver.caltech.edu/CaltechAUTHORS:20150929-091638824Permittivity of β-Ga_2O_3 at low frequencies
https://resolver.caltech.edu/CaltechAUTHORS:20150929-092908338
Year: 1971
DOI: 10.1016/0038-1101(71)90176-6
The relative dielectric constant ϵ_r of β-Ga_2O_3, in
the direction perpendicular to the (100) plane is
found to be 10.2 ±0.3. Within the measurement
error ϵ_r is the same at 297°K and at 77°K, and is
independent of frequency from 5 kHz to 500 kHz.https://resolver.caltech.edu/CaltechAUTHORS:20150929-092908338Power Schottky diode design and comparison with the junction diode
https://resolver.caltech.edu/CaltechAUTHORS:20150212-160010452
Year: 1971
DOI: 10.1016/0038-1101(71)90111-0
Because the Schottky diode is a one-carrier device, it has both advantages and disadvantages with respect to the junction diode which is a two-carrier device. The advantage is that there are practically no excess minority carriers which must be swept out before the diode blocks current in the reverse direction. The disadvantage of the Schottky diode is that for a high voltage device it is not possible to use conductivity modulation as in the pin diode; since charge carriers are of one sign, no charge cancellation can occur and current becomes space charge limited. The Schottky diode design is developed in Section 2 and the characteristics of an optimally designed silicon Schottky diode are summarized in Fig. 9. Design criteria and quantitative comparison of junction and Schottky diodes is given in Table 1 and Fig. 10. Although somewhat approximate, the treatment allows a systematic quantitative comparison of the devices for any given application.https://resolver.caltech.edu/CaltechAUTHORS:20150212-160010452Computers That Put the Power Where It Belongs
https://resolver.caltech.edu/CaltechAUTHORS:20150213-142621206
Year: 1972
In the next ten years almost every facet of our society will be automated to some degree. Whether this will be a change for the good or for the bad will depend on how it is done.https://resolver.caltech.edu/CaltechAUTHORS:20150213-142621206Electronic Current Flow Through Ideal Dielectric Films
https://resolver.caltech.edu/CaltechAUTHORS:20151007-110001781
Year: 1972
During the past few decades a large literature has accumulated on the subject of current flow through dielectric films. Much of this material contains detailed analyses of many physical effects and a
great deal of multiparameter curve fitting. Until recently all this activity had given the field a rather bad name, since it appeared that all effects were very complicated and nothing could be understood in a first-principles way. It is true, in fact, that in many thin-film
systems the current flow is dominated by impurities, trapping processes, and so on, so that no simple, clear picture emerges for the mechanism of current flow. However, in the past few years it has become clear that certain insulating materials behave in a nearly ideal
fashion and can be understood in a very simple and fundamental way.
In this chapter I shall not attempt to discuss the mass of literature dealing with data on dielectrics that were not well characterized and well understood. Instead, I shall concentrate on examples in which nearly ideal behavior was observed and in which the simple physics of the current-flow processes is clear. In retrospect it seems
obvious that much of the previous data is also understandable on rather simple grounds and that there were a number of conceptual errors that led to the belief that vastly complicated processes were involved. This is by no means true for all the data in the literature,
but certainly with good hindsight resulting from a clear understanding of ideal materials, a much better understanding of the nonideal cases
is also possible. Since the details of all the results I shall cite are available in the published literature, I shall discuss only the ideas and basic principles involved and give references where a more complete
discussion may be found.https://resolver.caltech.edu/CaltechAUTHORS:20151007-110001781Charge transfer in charge-coupled devices
https://resolver.caltech.edu/CaltechAUTHORS:20150114-110748689
Year: 1972
DOI: 10.1109/ISSCC.1972.1155057
Previous theoretical work on the operation of charge-coupled devices has been rather qualitative. These studies emphasize one of a number of factors which can influence the charge-transfer process, for example, nonlinear diffusion and fringing fields. However, none of these studies take account of all the factors in a realistic way.https://resolver.caltech.edu/CaltechAUTHORS:20150114-110748689Current-voltage characteristics of small size MOS transistors
https://resolver.caltech.edu/CaltechAUTHORS:20150126-163955527
Year: 1972
DOI: 10.1109/T-ED.1972.17428
One-dimensional analysis is used to find an upper and lower bound to the drain current of MOS transistors. The drain and source depletion regions and charge carrier velocity saturation are taken into account. These considerations are important in small devices.https://resolver.caltech.edu/CaltechAUTHORS:20150126-163955527Barrier Energies in MIM Structures from Photoresponse: Effect of Scattering in the Insulating Film
https://resolver.caltech.edu/CaltechAUTHORS:20141216-152524159
Year: 1972
DOI: 10.1063/1.1661392
Scattering of electrons photoexcited into the insulator conduction band prevents photoresponse from following the Fowler relation in MIM structures. However, barrier energies
can be obtained without specific knowledge of the scattering process either by measuring
the threshold for photo response directly, or by applying sufficiently large voltages across
the insulator.https://resolver.caltech.edu/CaltechAUTHORS:20141216-152524159Permittivity of Strontium Titanate
https://resolver.caltech.edu/CaltechAUTHORS:20141216-152948216
Year: 1972
DOI: 10.1063/1.1661463
The permittivity of single‐crystal single‐domain strontiumtitanate has been measured in detail in the [001], [011], and [111] directions, as a function of temperature (from 4.2 to 300 °K), electric field (from −23 000 to +23 000 V/cm, and frequency (from 1 kHz to 50 MHz). The free energy of the crystal is determined as a function of polarization with temperature as a parameter. The Curie‐Weiss law is satisfied in the temperature range 60–300 °K, giving a Curie temperature of 30 ± 2 °K for the three crystal orientations. The Lyddane‐Sachs‐Teller (LST) relation is satisfied for temperatures between 30 and 300 °K and for electric fields between 0 and 12 000 V/cm. A generalized LST relation is used to calculate the permittivity of strontiumtitanate from zero to optic frequencies. Two active optic modes are important. The lower‐frequency mode is attributed mainly to motion of the strontium ions with respect to the rest of the lattice, while the higher‐frequency active mode is attributed to motion of the titanium ions with respect to the oxygen lattice. The restoring forces that act on the Ti ions begin to "harden" when these ions are displaced approximately 0.002 Å from their equilibrium positions.https://resolver.caltech.edu/CaltechAUTHORS:20141216-152948216Fundamental limitations in microelectronics — I. MOS technology
https://resolver.caltech.edu/CaltechAUTHORS:20150212-160423500
Year: 1972
DOI: 10.1016/0038-1101(72)90103-7
The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain 'corner' breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10^7–10^8 MOS transistors per cm^2.https://resolver.caltech.edu/CaltechAUTHORS:20150212-160423500Limitations in Microelectronics - II. Bipolar Technology
https://resolver.caltech.edu/CaltechAUTHORS:20150927-233838341
Year: 1972
DOI: 10.1016/0038-1101(72)90026-3
The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.https://resolver.caltech.edu/CaltechAUTHORS:20150927-233838341Anomalous resonance of strontium titanate
https://resolver.caltech.edu/CaltechAUTHORS:20141216-151715740
Year: 1972
DOI: 10.1063/1.1660845
An anomalous resonance exhibited by perovskite strontium titanate crystals are obtained by cooling the samples with an
applied electric field. A plausible mechanism involves a mechanical oscillation with a frequency determined by the
domain boundary spacing. which is coupled to the electric field through the piezoelectric strain constant.https://resolver.caltech.edu/CaltechAUTHORS:20141216-151715740Surface barrier energies on strontium titanate
https://resolver.caltech.edu/CaltechAUTHORS:20141216-152028619
Year: 1972
DOI: 10.1063/1.1660984
The metal-semiconductor surface-barrier systems consisting of the metals gold, palladium, copper, or indium on
chemically prepared or cleaved strontium titanate surfaces have been investigated in detail. Surface-barrier energies have
been studied by photoresponse, forward current versus voltage, and thermal activation energy techniques yielding values
in excellent agreement with each other. Forward current-voltage characteristics ~ere in quantitative agreement with
simple diode thermionic theory as modified by the inclusion of image force lowering. The reverse current-voltage
characteristic of these stable barriers also is in agreement with that expected from thermionic theory including simple
image force lowering over a bias range from -0.1 to -4 V.https://resolver.caltech.edu/CaltechAUTHORS:20141216-152028619Push clocks: a new approach to charge-coupled devices clocking
https://resolver.caltech.edu/CaltechAUTHORS:MOHapl73
Year: 1973
DOI: 10.1063/1.1654600
A new approach to charge-coupled device clocking has been developed—dynamic push clocks. With dynamic push clocks, the charge is transferred by pushing it from one storage site to another. The push clock approach results in a larger signal dynamic range, larger signal-to-noise ratio, and better performance at both high and low frequencies.https://resolver.caltech.edu/CaltechAUTHORS:MOHapl73The influence of interface states on incomplete charge transfer in overlapping gate charge-coupled devices
https://resolver.caltech.edu/CaltechAUTHORS:20150113-162610060
Year: 1973
DOI: 10.1109/JSSC.1973.1050361
A simple and accurate model is used to estimate the incomplete charge transfer due to interface states trapping in the overlapping gate charge-coupled devices. It is concluded that trapping in the interface states under the edges of the gates parallel to the active channel limits the performance of the devices at moderate and low frequencies. The influence of the device parameters, dimensions, and clocking waveforms on the signal degradation is discussed. It is shown that increasing the clock voltages, reduces the incomplete charge transfer due to interface state trapping.https://resolver.caltech.edu/CaltechAUTHORS:20150113-162610060Charge transfer in overlapping gate charge-coupled devices
https://resolver.caltech.edu/CaltechAUTHORS:20150113-165257060
Year: 1973
DOI: 10.1109/JSSC.1973.1050376
A detailed numerical simulation of the free charge transfer in overlapped gate charge-coupled devices is presented. The transport are analyzed in terms of thermal diffusion, self-induced fields, and fringing fields under all the relevant electrodes and interelectrode regions with time-varying gate potentials. The results of the charge transfer with different clocking schemes and clocking waveforms are presented. The dependence of the stages of the charge transfer on the device parameters are discussed in detail. A lumped-circuit model of CCD that could be used to obtain the charge-transfer characteristics with various clocking waveforms is also presented.https://resolver.caltech.edu/CaltechAUTHORS:20150113-165257060The nature of the voltage-dependent conductance induced by alamethicin in black lipid membranes
https://resolver.caltech.edu/CaltechAUTHORS:20150109-141301409
Year: 1973
DOI: 10.1007/BF01868075
Alamethicin induces a conductance in black lipid films which increases exponentially with voltage. At low conductance the increase occurs in discrete steps
which form a pattern of five levels, the second and third being most likely. The conductance of each level is directly proportional to salt concentration, inversely proportional to solution viscosity, and nearly independent of voltage.
The probability distribution of the five steps is not a function of voltage, but as the voltage is increased, more levels begin to appear. These can be explained as superpositions of the original five, both in position and relative probability.
This suggests that the five levels are associated with a physical entity which we call a pore. This point of view is confirmed by the following measurements. The kinetic
response of the current to a voltage step is first order, and shows an exponential increase in rate of pore formation and an exponential decrease in rate of pore disappearance with voltage. If these rates are statistical, the number of pores should fluctuate about a voltage-dependent mean. High conductance current fluctuations are too large to be
explained by fluctuation in the number of pores alone. But if fluctuations among the five levels are included, the magnitude of the fluctuations at high conductance is accurately predicted.
Alamethicin adsorbs reversibly to the membrane surface, and the conductance at a fixed voltage depends on the ninth power of alamethicin concentration and on the
fourth power of salt concentration, in the aqueous phase. In our bacterial phosphatidyl ethanolamine membranes, alamethicin added to one side of the membrane produces
elevated conductance only when the voltage on that side is increased.https://resolver.caltech.edu/CaltechAUTHORS:20150109-141301409A barrier model for current flow in lipid bilayer membranes
https://resolver.caltech.edu/CaltechAUTHORS:20150109-143557131
Year: 1973
DOI: 10.1007/BF01869814
The shape of the energy barrier inside thin, insulating membranes can be an important factor in determining the detailed behavior of transmembrane ionic flows.
In particular, a model is developed in which the shape of the barrier is expected to have direct influence on such experimentally important membrane properties as: (a) the shape of the current-voltage relation; (b) the dependence of zero current conductivity on asymmetric
concentrations; (c) the dependence of the rectification ratio on the concentration ratio.
Current-voltage curves were measured for a wide range of symmetrical and asymmetrical concentrations in black lipid (phosphatidyl ethanolamine) films in the presence
of nonactin and potassium. A single barrier shape was found to describe accurately the experimental results in terms of the model.https://resolver.caltech.edu/CaltechAUTHORS:20150109-143557131ESP, A Distributed Architecture LSI Machine
https://resolver.caltech.edu/CaltechAUTHORS:20151008-160932933
Year: 1974
The Externally Sequenced Processor
(ESP) is a system which embodies a complete
separation of the control and data processing
functions of the machine. The ESP is
organized so that additional functional capabilities
as well as peripherals can be added.
The interfacing requirements are particularly
straightforward.https://resolver.caltech.edu/CaltechAUTHORS:20151008-160932933Electrical interface barriers
https://resolver.caltech.edu/CaltechAUTHORS:MCGjvst84b
Year: 1974
DOI: 10.1116/1.1318540
A review of the phenomena associated with electrical barriers between metals, and insulators and semiconductors is presented. The observed phenomenological rules governing the value of the barrier energies for different metals on the same insulator or semiconductor are presented. The barrier energies on ionic insulators are shown to vary strongly with the metal. While in the case of covalent semiconductors, the barrier energies are relatively independent of the metal. The barrier energy from the metal to the conduction band of the semiconductor is shown to be approximately two-thirds of the semiconductor band gap with certain exceptions. Transport through interfacial barriers is illustrated by discussing the transport through metal–GaSe–metal structures and Mg–SiO_2 structures. Both thermal induced transport over the barrier and tunneling through the barriers are discussed.https://resolver.caltech.edu/CaltechAUTHORS:MCGjvst84bSingle-Chip Cursive Character Generator
https://resolver.caltech.edu/CaltechAUTHORS:20150927-233249188
Year: 1975
DOI: 10.1109/ISSCC.1975.1155385
A unique circuit design using conventional MOS technology
has been found to yield a sequential read-only analog
memory which can generate the x- and y-axis deflection
voltages for the stroke-by-stroke synthesis of
alphanumeric characters.https://resolver.caltech.edu/CaltechAUTHORS:20150927-233249188A critical look at microprocessor architecture
https://resolver.caltech.edu/CaltechAUTHORS:20170808-170646928
Year: 1975
DOI: 10.1109/ISSCC.1975.1155410
LSI has provided machine designers a medium of unprecedented power and versatility. The potential of this technology has been doubling every year and promises to continue for another factor of 1000. It is inevitable that such potential will be used to achieve ever more powerful machine organizations and will, in the long run, totally change our basic concepts of machine structure and function. To date, however, the microprocessors which have been implemented are of a very conventional type. This trend poses several fundamental questions.https://resolver.caltech.edu/CaltechAUTHORS:20170808-170646928ESP, A Distributed Architecture LSI Machine
https://resolver.caltech.edu/CaltechAUTHORS:20151008-160109295
Year: 1976
The Externally Sequenced Processor (ESP) is a system that embodies a complete separation
of the control and data processing functions of the machine. The ESP is organized
so that additional functional capabilities as well as peripherals can be added. The
interfacing requirements are particularly straightforward.https://resolver.caltech.edu/CaltechAUTHORS:20151008-160109295Correlation for III-V and II-VI Semiconductors of the Au Schottky Barrier Energy with Anion Electronegativity
https://resolver.caltech.edu/CaltechAUTHORS:MCCprl76
Year: 1976
DOI: 10.1103/PhysRevLett.36.56
The Schottky barrier for holes on common III-V and II-VI semiconductors contacted by Au is shown to depend only on the anion electronegativity.https://resolver.caltech.edu/CaltechAUTHORS:MCCprl76A two's complement pipeline multiplier
https://resolver.caltech.edu/CaltechAUTHORS:20150120-163927542
Year: 1976
DOI: 10.1109/ICASSP.1976.1169990
A serial-data pipeline multiplier was designed and implemented in p-channel silicon-gate MOS. It uses a radix-4 Booth algorithm for two's complement compatibility. The circuit is modular, and is configured to multiply one data word by two coefficient words simultaneously.https://resolver.caltech.edu/CaltechAUTHORS:20150120-163927542Schottky barriers on compound semiconductors: The role of the anion
https://resolver.caltech.edu/CaltechAUTHORS:MCCjvst76
Year: 1976
DOI: 10.1116/1.568993
The Schottky barrier for holes on common III–V and II–VI semiconductors contacted by Au is shown to depend only on the anion. Compilation of the experimental data shows that compound semiconductors with the same anion but different cations possess very similar values for the the Au Schottky barrier for holes. Further, the data show that the Pauling electronegativity of the anion provides a useful ordering parameter for the height of the Schottky barrier. This correlation is compared with analogous barrier data on rocksalt and layer structures as well as earlier results for the semiconductor–vacuum interface.https://resolver.caltech.edu/CaltechAUTHORS:MCCjvst76Highly electronegative metallic contacts to semiconductors using polymeric sulfur nitride
https://resolver.caltech.edu/CaltechAUTHORS:20120808-132551604
Year: 1976
DOI: 10.1063/1.88868
The Schottky barriers formed on n‐ZnS and n‐ZnSe by polymeric sulfur nitride have been compared to barriers formed by Au. Barrier energies as determined by photoresponse, current‐voltage, and capacitance‐voltage methods show that (SN)_x is approximately 1.0 eV higher than Au on n‐ZnS and 0.3–0.4 eV higher than Au on n‐ZnSe. We believe that this is the first report of any metallic contact more electronegative than Au.https://resolver.caltech.edu/CaltechAUTHORS:20120808-132551604Schottky barrier heights on p-type diamond and silicon carbide (6h)
https://resolver.caltech.edu/CaltechAUTHORS:20141217-152744175
Year: 1976
DOI: 10.1016/0375-9601(76)90088-8
The Schottky barrier heights for Au, Al, and Ba on diamond are reported. The variation of the barrier energy with metals is found to be small. A previously incorrect report of S for SiC is corrected.https://resolver.caltech.edu/CaltechAUTHORS:20141217-152744175128-bit multicomparator
https://resolver.caltech.edu/CaltechAUTHORS:20150114-095719979
Year: 1976
DOI: 10.1109/JSSC.1976.1050799
A 128-bit multicomparator was designed to perform the search-sort function on arbitrary length data strings. Devices can be cascaded for longer block lengths or paralleled for bit-parallel, word-serial applications. The circuit utilizes a 3-phase static-dynamic shift register cell for data handling and a unique gated EXCLUSIVE-NOR circuit to accomplish the compare function. The compare operation is performed bit parallel between a `data' register and a `key' register with a third `mask' register containing DON'T CARE bits that disable the comparator. The multicomparator was fabricated using p-channel silicon-gate metal-oxide-semiconductor (MOS) technology on a 107/spl times/150 mil chip containing 3350 devices. With transistor-transistor logic (TTL) input, data rates in excess of 2 MHz have been attained. The average power dissipation was 250 mW in the dynamic mode and 300 mW in the static mode.https://resolver.caltech.edu/CaltechAUTHORS:20150114-095719979HgSe, a highly electronegative stable metallic contact for semiconductor devices
https://resolver.caltech.edu/CaltechAUTHORS:BESapl76
Year: 1976
DOI: 10.1063/1.89109
Schottky barriers formed by the highly electronegative substance HgSe on n-ZnS and on n-ZnSe have been characterized by capacitance-voltage and photoresponse measurements. The barriers are about 0.5 eV greater than Au barriers on these n-type substrates. HgSe contacts are stable under ambient conditions and are easily fabricated, making them attractive for device use.https://resolver.caltech.edu/CaltechAUTHORS:BESapl76Basic Limitations in Microcircuit Fabrication Technology
https://resolver.caltech.edu/CaltechAUTHORS:20150927-232217795
Year: 1976
This report presents the findings of a 6-month study undertaken for the Defense Advanced Research Projects Agency to ascertain what, if any, research ARPA might sensibly conduct in integrated microcircuit technology. The authors entered upon the study through a conviction that serious international competition in this technology may appear in the next few years, and a desire to ensure for the United States as favorable an opportunity to meet this competition as research can make available. Both the ubiquitous nature of micro-electronics in defense applications and the particularly severe special defense requirements for complex, low-power, micro-miniaturized circuitry make a commanding lead in this technology very important. The authors wished to assure themselves and ARPA that the existing research programs provide adequately for the forthcoming needs of the nation. The report details some high-leverage research areas, not now receiving government or private support, where relatively small, advanced research efforts may have substantial payoff. No endorsement of the study conclusions by ARPA is implied or intended.https://resolver.caltech.edu/CaltechAUTHORS:20150927-232217795Microelectronics and Computer Science
https://resolver.caltech.edu/CaltechAUTHORS:20150112-151034722
Year: 1977
The functional architecture of the computer has traditionally been shaped by the size of specialized components and concepts of how people think. Microelectronics is now eliminating these constraints.https://resolver.caltech.edu/CaltechAUTHORS:20150112-151034722Cost and Performance of VLSI Computing Structures
https://resolver.caltech.edu/CaltechAUTHORS:20150927-230413213
Year: 1978
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic
silicon chip. What will the nature of such systems be? How will they be designed? What will be their
cost and performance?
Conducting paths are required for communicating information throughout any integrated system. The
length and organization of these communication paths places a lower bound on the area and time required
for system operations. Optimal designs can be achieved in only a few of the many alternative structures.
A random access memory is analyzed in detail as an example. It is shown that in each case an optimum
design is possible, using the area - time product as a cost function.https://resolver.caltech.edu/CaltechAUTHORS:20150927-230413213A MOS cursive-character generator
https://resolver.caltech.edu/CaltechAUTHORS:20150114-104430588
Year: 1978
DOI: 10.1109/JSSC.1978.1052057
Cursive characters can be made to be more readable, more
attractive, and better suited to the operation of graphic CRT terminals than the usual dot-matrix type; a system using cursive-type characters achieves much higher writing rate while requiring much less bandwidth
than that using dot-matrix-type characters. This paper presents an economical method of generating the x, y, and z analog signals for forming cursive characters with the deflection system of a CRT.
A circuit design embodying a complete 48-stroke character generator on a single MOS integrated circuit is described. The IC accepts 7-bit ASCII code and outputs x, y, and z analog signals to generate any one of 32 standard ASCII characters in 5 μs. Additional groups of 32
characters can be added by merely paralleling additional chips. The entire 32 character digital and analog function has been implemented on a single self-contained 16-pin silicon-gate MOS chip 125 X 165 mil in size. Character encoding on the chip is accomplished in one mask at
the diffusion step, and a straightforward mask-generation procedure has been developed.https://resolver.caltech.edu/CaltechAUTHORS:20150114-104430588VLSI and Technological Innovation
https://resolver.caltech.edu/CaltechAUTHORS:20150213-105251082
Year: 1979
VLSI relies on a range of disciplines for its successful implementation. Two of the most important of these are still in their infant stages. A. Design methodologies to manage complexity. B. Architecture of ultra concurrent machines. Innovation in infant disciplines occurs most rapidly and successfully when a large number of small groups proceed independently under the motivation of market opportunity. In a few years, a substantial fraction of the engineering work force will have a working knowledge of LSI design. At the same time, fabrication areas are becoming more and more capital intensive. What is needed is a clean, standard interface between a multitude of small diverse VLSI design groups and a few state-of-the-art fabrication suppliers. A proposal for such an interface is presented in this article.https://resolver.caltech.edu/CaltechAUTHORS:20150213-105251082Cost and performance of VLSI computing structures
https://resolver.caltech.edu/CaltechAUTHORS:20150114-100150657
Year: 1979
DOI: 10.1109/JSSC.1979.1051197
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time product as a cost function.https://resolver.caltech.edu/CaltechAUTHORS:20150114-100150657Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems
https://resolver.caltech.edu/CaltechAUTHORS:20150126-164740990
Year: 1979
DOI: 10.1109/T-ED.1979.19458
ransmission of signals on large capacitance paths in a VLSI system may result in substantial degradation of the overall system performance. In this paper minimization of the delay times associated with driving and sensing signals from large capacitance paths by optimizing the fan-out factor of the driver stages, the gain of the input sensing stages, and the path voltage swing are examined. Examples of driving signals on a high capacitance path with two driving schemes are: a push-pull depletion-load driver chain and a fixed driver; and of sensing signals with two sensing schemes: a single-ended depletion-load inverter input stage and a balanced regenerative strobed latch are presented. We conclude that minimum delay time is achieved when the delay times of the successive stages of the driver chain, the high capacitance path, and the input sensing stage are comparable. In general, transmission time of signals in a system is minimized when the delay times of the different stages of the system are comparable.https://resolver.caltech.edu/CaltechAUTHORS:20150126-164740990Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems
https://resolver.caltech.edu/CaltechAUTHORS:20150114-102206258
Year: 1979
DOI: 10.1109/JSSC.1979.1051198
Minimization of the delay times associated with driving and sensing signals from large capacitance paths by optimizing the fan-out factor of the driver stages, the gain of the input sensing stages, and the path voltage swing are examined. Examples of driving signals on a high capacitance path with two driving schemes are: a push-pull depletion-load driver chain and a fixed driver; and of sensing signals with two sensing schemes: a single-ended depletion-load inverter input stage and a balanced regenerative strobed latch are presented.https://resolver.caltech.edu/CaltechAUTHORS:20150114-102206258Cost and Performance of VLSI Computing Structures
https://resolver.caltech.edu/CaltechAUTHORS:20150126-164326834
Year: 1979
DOI: 10.1109/T-ED.1979.19457
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time product as a cost function.https://resolver.caltech.edu/CaltechAUTHORS:20150126-164326834The Impact of VLSI on Computer Science Education
https://resolver.caltech.edu/CaltechAUTHORS:20150127-163141287
Year: 1979
DOI: 10.1109/TE.1979.4321288
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150127-163141287Introduction to VLSI Systems
https://resolver.caltech.edu/CaltechAUTHORS:20141215-164154773
Year: 1980
[No abstract]https://resolver.caltech.edu/CaltechAUTHORS:20141215-164154773Challenges Raised by VLSI Technology
https://resolver.caltech.edu/CaltechAUTHORS:20151008-152636094
Year: 1980
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20151008-152636094VLSI and Technological Innovations
https://resolver.caltech.edu/CaltechAUTHORS:20150927-230856422
Year: 1981
Rather than innovation in general, I will discuss what I believe
to be the most important opportunity since the industrial
revolution, rivalling it in significance. This unique circumstance
is created by the emerging Very Large Scale Integrated
(VLSI) technology, with which enormously complex digital
electronic systems can be fabricated on a single chip of
Silicon one-tenth the size of a postage stamp. Out of it
systems will be created which radically change our modes of
communication, commerce, education, entertainment, science and
the underlying rate of cultural evolution. The quality of
human life can be improved in remarkable ways by these changes.
Electronics creates no noxious by-products and uses only miniscule
amounts of energy. It can accomplish tasks which were
previously energy intensive, and dangerous or degrading to
human workers. There is no doubt that this electronic revolution
will take place.https://resolver.caltech.edu/CaltechAUTHORS:20150927-230856422Cost and Performance of VLSI Computing Structures
https://resolver.caltech.edu/CaltechAUTHORS:20150223-143648166
Year: 1981
Using VLSI technology, it will soon be possible to implement
entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of
the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time
product as a cost function.https://resolver.caltech.edu/CaltechAUTHORS:20150223-143648166A Notation for Designing Restoring Logic Circuitry in CMOS
https://resolver.caltech.edu/CaltechAUTHORS:20150213-104643106
Year: 1981
We introduce a programming notation in which every syntactically correct program specifies a restoring logic component, i.e., a component whose outputs are permanently connected, via "not too many" transistors, to the power supply. It is shown how the specified components can be translated into transistor diagrams for CMOS integrated circuits . As these components are designed as strict hierarchies, it is hoped that the translation of the transistor diagrams into layouts for integrated circuits can be accomplished mechanically.https://resolver.caltech.edu/CaltechAUTHORS:20150213-104643106Bit-Serial Inner Product Processors in VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150212-162610645
Year: 1981
In this paper we describe a bit-serial pipelined implementation of an inner product processor, and related interconnections of a number of such processors on a single chip. We argue that bit-serial computational models are particularly suited for VLSI, because of relatively inexpensive communication links and arithmetic processing elements, in terms of the area occupied on silicon. Sixteen inner product processors, described here, may be easily placed on a single 40-pin chip in today's NMOS technology with a 2 micron lambda. Similar arguments for bitserial arithmetic were used in [3]. in a description of a design of a general purpose massively parallel processor.https://resolver.caltech.edu/CaltechAUTHORS:20150212-162610645Minimum Propagation Delays in VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150213-103145341
Year: 1981
With feature sizes decreasing and chip area increasing it becomes more and more time consuming to transport signals over long distances across the chip [5]. Designers are already introducing more levels of metal connections, using wider and thicker paths for longer distances. Another recent development is the introduction of an additional level of connections between the chip and the pc-board, multilayer ceramic chip carriers. The trend is undoubtedly towards even more connecting levels. In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light.https://resolver.caltech.edu/CaltechAUTHORS:20150213-103145341Minimum Propagation Delays in VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20120423-103239364
Year: 1982
DOI: 10.7907/7w91m-s9v80
Conditions are outlined under which propagation delays in
VLSI circuits can be achieved that are logarithmic in the wire lengths. These conditions are imposed by area requirements and the velocity of light.https://resolver.caltech.edu/CaltechAUTHORS:20120423-103239364A notation for designing restoring logic circuitry in CMOS
https://resolver.caltech.edu/CaltechAUTHORS:20150313-133632708
Year: 1982
DOI: 10.1016/S0026-2692(82)80130-4
A program notation is introduced together with a technique for translating programs in
that notation into transistor diagrams for CMOS integrated circuits. A number of
restrictions are imposed on the programs ensuring every circuit thus obtained to be
restoring. The program notation caters to hierarchical design. It is shown how the
observance of the restrictions can be checked for each level of the hierarchy separately.
The techniques discussed in this paper may be viewed as a modest step towards silicon
compilation.https://resolver.caltech.edu/CaltechAUTHORS:20150313-133632708Formal Specification of Concurrent Systems
https://resolver.caltech.edu/CaltechCSTR:1982-5042-tr-82
Year: 1982
DOI: 10.7907/kmq8e-ezn08
No Abstract.https://resolver.caltech.edu/CaltechCSTR:1982-5042-tr-82Minimum propagation delays in VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150114-102708301
Year: 1982
DOI: 10.1109/JSSC.1982.1051810
Conditions are outlined under which propagation delays in VLSI circuits can be achieved that are logarithmic in the wire lengths. These conditions are imposed by area requirements and the velocity of light.https://resolver.caltech.edu/CaltechAUTHORS:20150114-102708301Silicon compilers and foundries will usher in user-designed VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150108-132537509
Year: 1982
New design methodologies will exploit chip complexity with concurrent systems; architecture and algorithms will entwine on the chip.https://resolver.caltech.edu/CaltechAUTHORS:20150108-132537509VLSI Circuit as Communicating Processes: A Universal Simulator
https://resolver.caltech.edu/CaltechAUTHORS:20150223-144315648
Year: 1983
A VLSI system is represented as a hierarchy of
modules. These modules range from analog models
of circuit elements to systems such as systolic arrays
and tree machines. Though these elements are of
drastically different natures, they share the property
of being autonomous processes, each performing a sequence
of events and communicating with one another.
This metaphor has been developed as a formal model
of computation; any computational system can be
described in these terms. We describe a simulator
which is built upon this metaphor. Central to the
simulator is a fixed-point algorithm which finds the
steady state of the system. Since in both theory and
practice it is capable of handling all levels of design,
we call it a universal simulator.https://resolver.caltech.edu/CaltechAUTHORS:20150223-144315648Concurrent Algorithms as Space-time Recursion Equations
https://resolver.caltech.edu/CaltechAUTHORS:20150318-140330182
Year: 1983
In this paper, we describe a methodology and a single notation for the specification
and verification of synchronous and self-timed concurrent systems ranging from the level
of transistors to communicating processes. The uniform treatment of these systems results
in a powerful abstraction mechanism which allows management of system complexity.https://resolver.caltech.edu/CaltechAUTHORS:20150318-140330182Structural and Behavioral Composition of VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150310-154750071
Year: 1983
VLSI design requires all of the complexity management discipline associated with complex
software systems, but without the underlying simplicity of a single sequential machine. Not only must we deal with the problems of enormous concurrency, but we
must map the entire design onto a physical medium, with real constraints on space, time,
and energy imposed by the laws of physics.https://resolver.caltech.edu/CaltechAUTHORS:20150310-154750071A Hierarchical Simulator Based on Formal Semantics
https://resolver.caltech.edu/CaltechAUTHORS:20120420-111744031
Year: 1983
DOI: 10.7907/jz6sz-1pt23
N/Ahttps://resolver.caltech.edu/CaltechAUTHORS:20120420-111744031A Hierarchical Simulator Based on Formal Semantics
https://resolver.caltech.edu/CaltechAUTHORS:20150130-160953426
Year: 1983
Simulation consists of exercising the representation of a design on a general purpose computer. It differs from programming only because the ultimate implementation will be in a different medium, say a VLSI chip. In order for simulation to be in any sense effective, the simulated
system must perform the same function as the ultimate implementation. A VLSI chip is a highly concurrent object; the simulation of such a chip amounts to programming a highly concurrent system. It follows that any
demonstrably correct simulation technique will be one of the two types:
(1) The entire design is represented as an implementation with objects which are abstract models of the medium at the bottom level (e.g. transistor model). The simulation operates on a representation which is a direct image of the fully instantiated implementation in the medium.
(2) The design is represented as a hierarchy of implementations. Each level of implementation is constructed of objects which are abstract models of the implementation at the level below it. The
simulation operates on a hierarchical representation where each level is refined by the level below it.https://resolver.caltech.edu/CaltechAUTHORS:20150130-160953426Pooh: A Uniform Representation For Circuit Level Designs
https://resolver.caltech.edu/CaltechAUTHORS:20150310-155318797
Year: 1983
This paper describes a simple but general, technology independent representation for VLSI circuits which maintains connectivity, circuit schematic, and mask geometry
information. A transistor level cell is represented as the interconnection of devices along with their types, sizes and placement, and the cell's typed ports. Connection is represented explicitly by shared connection points. A file of technology dependent information indicates how to implement each transistor type, interconnect type and connection point type, as well as how structure types may
interact.https://resolver.caltech.edu/CaltechAUTHORS:20150310-155318797Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits
https://resolver.caltech.edu/CaltechCSTR:1983.5089-tr-83
Year: 1983
DOI: 10.7907/h46fc-bcr96
Modeling digital MOS circuits by RC networks has become a well accepted practice for estimating delays. In 1981, Penfield and Rubinstein proposed a method to bound the
delays of the nodes in an RC tree network. In this paper, we address the problem of dynamic timing simulation under RC-based models. Based upon the delay of Elmore, a
single value of delay is derived for any node in a general RC network. The effects of parallel
connections and stored charges are properly taken into consideration. The algorithm can
be used either as a stand-alone simulator, or as a front end for producing initial waveforms
for waveform-relaxation based circuit simulators. An experimental simulator called SDS
(Signal Delay Simulator) has been developed. For all the examples tested so far, this
simulator runs about two to three orders of magnitude faster than SPICE, and detects all
transitions and glitches at approximately the correct time.https://resolver.caltech.edu/CaltechCSTR:1983.5089-tr-83Minimum propagation delays in VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20120420-104637505
Year: 1983
DOI: 10.7907/xzm6p-fzr13
In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in
effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the
propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light.https://resolver.caltech.edu/CaltechAUTHORS:20120420-104637505Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits
https://resolver.caltech.edu/CaltechAUTHORS:20150217-161323301
Year: 1984
Modeling digital MOS circuits by RC networks has
become a well accepted practice for estimating delays.
In 1981, Penfield and Rubinstein proposed a method
to bound the waveforms of nodes in an RC tree network.
In this paper, a single value of delay is derived
for any node in a general RC network. The effects of
parallel connections and stored charges are properly
taken into consideration. The algorithms can be
used either as a stand-alone simulator, or as a front
end for producing initial waveforms for waveform-relaxation
based circuit simulators. An experimental
simulator called SDS (Signal Delay Simulator) has
been developed. For all the examples tested so far,
this simulator runs two to three orders of magnitude
faster than SPICE, and detects all transitions and
glitches at approximately the correct time.https://resolver.caltech.edu/CaltechAUTHORS:20150217-161323301A Correlating Optical Motion Detector
https://resolver.caltech.edu/CaltechAUTHORS:20150310-155720165
Year: 1984
Here we describe an optical motion detector that uses
integrated light sensors and analog and digital processing on the same chip. An image of an arbitrary scene or working
surface is sensed by an array of photodiodes, stored, and
correlated with the next image taken on the next cycle.
The position of maximum correlation indicates the relative
motion of the image during the time between samples. This
peak is detected using mutual inhibition and is converted to
digital signals that go off chip to indicate motion. This single
chip motion detector has application in optical mouse
systems. It overcomes certain limitations of present devices
which require a special operating surface. Other potential
uses are in automated vision systems and robotics. This
motion detector could be used, for example, to track parts
moving down an assembly line. We have built a
one-dimensional motion detector and shown it to work in the
laboratory. The design of a two-dimensional version is in
progress.https://resolver.caltech.edu/CaltechAUTHORS:20150310-155720165The Wolery
https://resolver.caltech.edu/CaltechCSTR:1984.5113-tr-84
Year: 1984
DOI: 10.7907/43z52-rx643
No Abstract.https://resolver.caltech.edu/CaltechCSTR:1984.5113-tr-84A VLSI Architecture for Sound Synthesis
https://resolver.caltech.edu/CaltechCSTR:1984.5158-tr-84
Year: 1984
DOI: 10.7907/3d575-yvm11
No Abstract.https://resolver.caltech.edu/CaltechCSTR:1984.5158-tr-84Correction to "Minimum Propagation Delays in VLSI"
https://resolver.caltech.edu/CaltechAUTHORS:20150114-104916717
Year: 1984
DOI: 10.1109/JSSC.1984.1052104
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150114-104916717An electronic model of the y-system of mammalian retina
https://resolver.caltech.edu/CaltechAUTHORS:20220523-171311035
Year: 1984
<p>A set of detailed circuits are described that implement what we believe to be a reasonably faithful model of the y-system of the retina. The model is shown in block-diagram form in Fig. 1. It consists of: 1. An array of receptors, R, such as those described in DF5121. 2. A resistive network with capacitance to ground, modeling the horizontal cells. The horizontal resistors, H, provide lateral conductance that can be loosely thought of as a model of the gap-junctions between cells. The cell capacitances are modeled as lumped elements. 3. Triad synapses, TS, that take the difference between the potential of the horizontal network and that receptor output, and drag the local potential of the horizontal network along in the process. 4. Bipolar cells, B, that threshold the output of the triad synapses and carry the signal forward. 5. Amacrine cells, A, that sum an asymmetric surround of bipolar outputs. 6. Receptive field units, RFU, that apply the amacrine inhibition to the bipolar outputs. 7. A dendritic network, DN, in which a number of receptive fields are summed. 8. The Ganglion cell proper, G, that integrates the DN sum with respect to time, and issues an output pulse if the integral exceeds some threshold.</p>https://resolver.caltech.edu/CaltechAUTHORS:20220523-171311035Signal Delay in General RC Networks
https://resolver.caltech.edu/CaltechAUTHORS:20150120-165111914
Year: 1984
DOI: 10.1109/TCAD.1984.1270090
Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charge are properly taken into consideration. A technique called tree decomposition and load redistribution is introduced that is capable of dealing with general RC networks without sacrificing a number of desirable properties of tree networks. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time.https://resolver.caltech.edu/CaltechAUTHORS:20150120-165111914A VLSI Approach to Sound Synthesis
https://resolver.caltech.edu/CaltechAUTHORS:20150223-141325251
Year: 1985
We present a VLSI approach to the generation of musical
sounds. This approach allows the generation of very
rich musical sounds using models that are easy to control
and have parameters corresponding to physical attributes
of musical instruments.
Past efforts in musical sound generation have been plagued
with several problems. The computational bandwidth that
is needed to compute musical sounds is enormous, and it is
hopeless to compute sounds in real time on a conventional
general purpose computer. An even larger problem with
previous efforts is the massive bandwidth needed for control
and update of parameters.
Sounds that come from physical sources are naturally represented by differential equations in time. Since there is a straight-forward correspondence between differential equations and finite difference equations, we can model musical instruments as simultaneous finite difference equations. Musical sounds can be produced by solving, in real time, the difference equations that model instruments.
A natural architecture for solving finite difference equations is one with an interconnection matrix between processors that can be reconfigured or "programmed". A realization of a new instrument involves reconfiguring the connection matrix between the processing elements along with configuring connections to the outside world both for control and updates of parameters.
For our basic unit of computation we have chosen a unit we
call a UPE (Universal Processing Element) - it computes
the function:
A + BM + (1 - M)D
We have implemented in nMOS technology a prototype systems
of UPEs and have been successful in implementing
some simple musical instruments on the system of UPEs.https://resolver.caltech.edu/CaltechAUTHORS:20150223-141325251A Novel Associative Memory Implemented Using Collective Computation
https://resolver.caltech.edu/CaltechAUTHORS:20150310-154028014
Year: 1985
A radically new type of associative memory, the ASSOCMEM, has been implemented in VLSI and tested. Analog circuit techniques are used to construct a network that evolves towards fully restored (digital) fixed-points that are the memories of the system. Association occurs
on the whole source word, each bit of which may assume a continuous analog value. The network does not require the distinction of a search key from a data field in either the source or target words. A key may be dynamically defined by differentially weighting any subset of the source
word. The key need not be exact; the system will evolve to the closest memory. In the case when the key is the whole input word, the system may be thought of as performing error correction.https://resolver.caltech.edu/CaltechAUTHORS:20150310-154028014A Methodology for Hierarchical Simulation and Verification of VLSI Systems
https://resolver.caltech.edu/CaltechAUTHORS:20150217-155711452
Year: 1985
We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodology allows (1) a design be decomposed in such a way that more efficient simulation algorithms than
those appeared in most one-level simulators can be employed, (2) abstraction of parts of a design may be
made to reduce the complexity of the entire design. We first give computation models of VLSI designs.
From these models , we derive appropriate algorithms and compare them to illustrate the power of our
methodology. Finally we present the method for ensuring correctness of design at each hierarchical level
and across different levels.https://resolver.caltech.edu/CaltechAUTHORS:20150217-155711452Concurrent Algorithms as Space-Time Recursion Equations
https://resolver.caltech.edu/CaltechAUTHORS:20150302-152631114
Year: 1985
Recent developments in the technology of fabricating large-scale integrated circuits have made it possible to implement computing systems that use many hundred
thousands of transistors to achieve a given task. An interesting design will have high computational complexity rather than merely vast numbers of identical simple components such as memory elements. Such a design can be represented as a fully instantiated implementation of objects of the implementation medium (e.g., transistors
in VLSI technology) or as successive hierarchical levels of implementations where each level is constructed of objects which are abstract models of the implementation
at the level below it. The former allows implementation details at the bottom level to penetrate throughout the whole design. Such representation may be
suited for machine execution but is hard to deal with from the designer's point of view, and verifying both its functionality and physical layout is costly. As the
complexity of the design grows, the limitation of this approach becomes more apparent. The second approach is aimed at managing the complexity of a design.
One breaks the design into successive levels of subsystems until each is of a manageable complexity-the hierarchical design method [11].https://resolver.caltech.edu/CaltechAUTHORS:20150302-152631114A VLSI Architecture for Sound Synthesis
https://resolver.caltech.edu/CaltechAUTHORS:20150217-164817869
Year: 1985
Sounds that come from physical sources are naturally represented by differential equations in time. Since there is a straightforward correspondence between differential equations in time and finite difference equations, we can
model musical instruments as simultaneous finite difference equations. Musical sounds can be produced by solving the difference equations that model instruments in real time.https://resolver.caltech.edu/CaltechAUTHORS:20150217-164817869A Sensitive Electronic Photoreceptor
https://resolver.caltech.edu/CaltechAUTHORS:20150310-153332443
Year: 1985
The photoreceptors in biological systems give meaningful outputs over about six orders of magnitude of illumination intensity. If we are to build an electronic vision system that is truly useful, it must have a similar dynamic range. The elements of an electronic receptor with many orders of magnitude dynamic range are described below. Experimental
devices were fabricated in p-well cMOS bulk technology through the MOSIS foundry; npn phototransistors with collector connected to substrate are a byproduct of this process. The n-type bulk forms the collector, the p-well is the base, and the n+ diffusion the emitter. In a
typical process, a large transistor of this sort has a current gain β of more than a thousand. Smaller transistors have lower current gains, but are still respectable. The key to very sensitive receptors is to use the current
gain of this very clean bipolar transistor before subjecting the signal to any noise from subsequent amplification stages.https://resolver.caltech.edu/CaltechAUTHORS:20150310-153332443A New Discipline for CMOS Design: an Architecture for Sound Synthesis
https://resolver.caltech.edu/CaltechAUTHORS:20150223-142831844
Year: 1985
A number of logic forms and clocking schemes for cMOS integrated circuits are in common use. The most common logic form consists of two networks of transistors, the gates of which are connected to the input variables.
An n-channel network defines the boolean condition under which the output is connected to ground (logic zero). A p-channel network defines the complementary condition under which the output is connected to a logical one. Since in many cMOS processes the output of a single
pass transistor cannot be guaranteed to exceed the logic threshold of a typical inverter, pass transistor networks are either forbidden or a complementary transmission gate employing both p and n-channel devices is used.
Clocking schemes for cMOS presently offer tradeoffs over a wide range in the risk vs efficiency space. In one scheme, a single phase clock and its complement are distributed, and used to control either transmission
gates or transistors controlling power to the p and n-channel switching networks. Proper operation in either case requires that the logic delay of the stage exceeds the skew between the two clock lines. In a much safer approach, a two-phase clock is used, both the clock and its complement
being distributed for each phase. In this case risk is eliminated at the expense of doubling the clock wiring. Yet another form is popular in gate-level designs. A single clock is distributed, and locally inverted at masterslave
storage elements. Risk in this case is eliminated at the expense of a minimum storage element employing ten or more transistors.
In this paper we describe a logic form that retains much of the simplicity, elegance, and compactness of the familiar 2-phase nMOS form, with the added advantage of fully static operation. Formal semantics for circuits implemented in this form are easily derived without detailed
circuit or switch-level simulation.https://resolver.caltech.edu/CaltechAUTHORS:20150223-142831844An Integer Based Hierarchical Representation for VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150112-140550704
Year: 1986
Geometries with 45° line segments are often used in integrated circuit layouts, since they can save considerable area. In the limit, the introduction of 45° lines is only 5% less dense than optimal geometry, i.e. circular geometry, whereas manhattan geometry is 27% less dense [7]. Obviously any actual design cannot
make use of this density factor everywhere - but figure 1 illustrates a simple but common routing problem where the introduction of 45° wires substantially
reduces the area. There has been a trend towards strict manhattan geometries in recent years, however, since it is commonly believed that design rule checking
is complicated by the inclusion of intermediate angles [11, 1, 3, 6]. This paper describes a hierarchical representation that supports a complete circuit description,
but restricts the set of allowable lines to be horizontal, vertical and 45°. Points are constrained to lie on an integer grid. Rather than use arbitrary polygons,
transistors and connection wires are constructed from paths whose sides and ends are created from an octagonal circle approximation. The geometry for contacts is
octagonal and is generated from the same circle approximation. The integer grid and restricted line styles allow the simplification of all the Geometrical Design
Rule (GDR) checking algorithms - for example a square root is not required in the point-point distance calculations, and division is never required. In fact this approach requires less computation than typical manhattan systems. All of the calculations that normally require real number representation are expressed in integers, eliminating any possibility of round-off errors.https://resolver.caltech.edu/CaltechAUTHORS:20150112-140550704An Integrated Analog Optical Motion Sensor
https://resolver.caltech.edu/CaltechAUTHORS:20150927-224806484
Year: 1986
This paper describes the theory and implementation of an integrated system that
reports the uniform motion of a visual scene. We have built a VLSI circuit that
reports the motion of an image focused directly on it. The chip contains an integrated
photosensor array to sense the image and has closely coupled custom circuits to perform
computation and data extraction.https://resolver.caltech.edu/CaltechAUTHORS:20150927-224806484A Hierarchical Timing Simulation Model
https://resolver.caltech.edu/CaltechAUTHORS:20150123-155931107
Year: 1986
DOI: 10.1109/TCAD.1986.1270186
A hierarchical timing simulation model has been developed
to deal with VLSI designs at any level of representation. A set of physically based parameters are used to characterize the behavior and timing of a semantic design object (cell) independent of its composition
environment. As cells are composed, the parameters of the composite cell can be determined from those of the component cells either analytically
or by simulation. Based on this model, a behavior-level simulator has been developed and combined with other tools to form an integrated design system that fully supports the structured design methodology.https://resolver.caltech.edu/CaltechAUTHORS:20150123-155931107VLSI architectures for implementation of neural networks
https://resolver.caltech.edu/CaltechAUTHORS:20141215-164438997
Year: 1986
DOI: 10.1063/1.36247
A large scale collective system implementing a specific model for associative memory was described by Hopfield [1]. A circuit model for this operation is illustrated in Figure 1, and consists of three major components. A collection of active gain elements (called amplifiers or "neurons") with gain function V = g(v) are connected by a passive interconnect matrix which provides unidirectional excitatory or inhibitory connections ("synapses") between the output of one neuron and the input to another. The strength of this interconnection is given by the
conductance G_(ij) = G_0T_(ij). The requirements placed on the gain function g(v) are not very severe [2], and easily met by VLSI-realizable amplifiers. The third circuit element is the capacitances that determine the time evolution of the system, and are modelled as lumped capacitances.
This formulation leads to the equations of motion shown in Figure 2, and to a Liapunov energy function which determines the dynamics of the system, and predicts the location of stable states (memories) in the case of a symmetric matrix T.https://resolver.caltech.edu/CaltechAUTHORS:20141215-164438997Modelling and simulation of integrated circuits
https://resolver.caltech.edu/CaltechAUTHORS:20141223-110109001
Year: 1986
DOI: 10.1016/0010-4485(86)90003-5
Describing integrated circuits based on their physical and topological properties leads naturally to efficient algorithms and device models for circuit simulation. Physically based relaxation algorithms exploit the local and sparse nature of the circuit interconnect. Models that directly represent the processes of charge flow extend naturally to integrated circuit devices allowing the distributed nature of the integrated transistor to be represented. This approach has been used to develop models for metal oxide semiconductors (MOS) and bipolar transistors. The model for the bipolar transistor has been generalized to describe the multicollector merged device structures of integrated injection logic.https://resolver.caltech.edu/CaltechAUTHORS:20141223-110109001A Physical Charge-Controlled Model for MOS Transistors
https://resolver.caltech.edu/CaltechAUTHORS:20150203-154214722
Year: 1987
As MOS devices scale to submicron lengths, short-channel effects become more pronounced, and an improved transistor model becomes a necessary tool for the VLSI designer [10]. We present a simple, physically based charge-controlled model. The current in the MOS transistor is described in terms of the mobile charge in the channel, and incorporates the physical processes of drift and diffusion. The
effect of velocity saturation is included in the drift term. We define a complete set of natural units for velocity, voltage, length, charge, and current. The solution of the dimensionless current-flow equations using
these units is a simple continuous expression, equally applicable in the subthreshold, saturation, and "ohmic" regions of transistor operation, and suitable for computer simulation of integrated circuits. The model is in agreement with measurements on short-channel transistors
down to 0.35μ channel length.https://resolver.caltech.edu/CaltechAUTHORS:20150203-154214722SeeHear
https://resolver.caltech.edu/CaltechAUTHORS:20151007-111205800
Year: 1987
The SeeHear is a system designed to help the blind. The heart of the system is a single custom
chip upon which an image is projected by a lens. The function of the system is to map visual
signals from moving objects in the image into auditory signals that can be projected through
earphones to a listener. A sensation is evoked similar to that which the listener would experience
if the moving objects were emitting sound. We hope that the auditory signals provided by the
SeeHear device, in addition to the sound cues already present in the environment, will enable
blind people to create a more detailed internal model of their surroundings than that which can
be extracted from naturally occuring sound cues alone.https://resolver.caltech.edu/CaltechAUTHORS:20151007-111205800Real-Time Visual Computations Using Analog CMOS Processing Arrays
https://resolver.caltech.edu/CaltechAUTHORS:20150203-152114654
Year: 1987
Integration of photosensors and processing elements provides a mechanism to concurrently perform computations previously intractable in real-time. We have used this approach to model biological early vision
processes. A set of VLSI "retina" chips have been fabricated, using large scale analog circuits (over lOOK transistors in total). Analog processing provides sophisticated, compact functional elements,
and avoids some of the aliasing problems encountered in conventional sampled-data artificial vision systems.https://resolver.caltech.edu/CaltechAUTHORS:20150203-152114654Neural Hardware for Vision
https://resolver.caltech.edu/CaltechAUTHORS:20150213-142420573
Year: 1987
A "retina" on a semiconductor chip simulates neurobiological processes.https://resolver.caltech.edu/CaltechAUTHORS:20150213-142420573A silicon retina for computing local edge orientations
https://resolver.caltech.edu/CaltechAUTHORS:20150313-133252018
Year: 1988
DOI: 10.1016/0893-6080(88)90503-5
Carver Mead has demonstrated the suitability of VLSI arrays of photoreceptors and
analog CMOS processing circuitry (so-called silicon retinas) for doing early vision processing.
So far, chips have been built that perform center-surround (X-system) and motion
detection (Y-system) operations. This Paper describes a chip which was designed to perform
a low level of image feature extraction: orientation selectivity.https://resolver.caltech.edu/CaltechAUTHORS:20150313-133252018Orientation-Selective VLSI Retina
https://resolver.caltech.edu/CaltechAUTHORS:20151012-141538820
Year: 1988
DOI: 10.1117/12.969056
In both biological and artificial pattern-recognition systems, the detection of oriented light-intensity edges is an important preprocessing step. We have constructed a silicon VLSI device containing an array of photoreceptors with additional hardware for computing center-surround (edge-enhanced) response as well as edge orientation at every point in the receptor lattice. Because computing the edge orientations in the array local to each photoreceptor would have made each pixel-computation unit too large (thereby reducing the resolution of the device), we devised a novel technique for computing the orientations outside of the array. All the transducers and computational elements are analog circuits made with a conventional CMOS process.https://resolver.caltech.edu/CaltechAUTHORS:20151012-141538820Computing Motion Using Resistive Networks
https://resolver.caltech.edu/CaltechAUTHORS:20160107-154149599
Year: 1988
To us, and to other biological organisms, vision seems effortless. We open
our eyes and we "see" the world in all its color, brightness, and movement.
Yet, we have great difficulties when trying to endow our machines with similar
abilities. In this paper we shall describe recent developments in the theory of
early vision which lead from the formulation of the motion problem as an ill-posed
one to its solution by minimizing certain "cost" functions. These cost
or energy functions can be mapped onto simple analog and digital resistive
networks. Thus, we shall see how the optical flow can be computed by injecting
currents into resistive networks and recording the resulting stationary voltage
distribution at each node. These networks can be implemented in cMOS VLSI
circuits and represent plausible candidates for biological vision systems.https://resolver.caltech.edu/CaltechAUTHORS:20160107-154149599A Two-Dimensional Visual Tracking Array
https://resolver.caltech.edu/CaltechAUTHORS:20150112-121106664
Year: 1988
The density and concurrency available in VLSI make it an excellent technology
for implementing visual image-processing. By incorporating phototransistors
and analog processing elements onto a single die, the large signal
bandwidths required for real-time computations can be achieved. This
paper describes a VLSI chip that computes the "center of intensity" of a
two-dimensional visual field. One application for this network is the localization
of a bright spot of light against a dark background. Theoretical and
experimental results are presented to describe the operation of the system
and its suitability as a input device for tracking servo systems.https://resolver.caltech.edu/CaltechAUTHORS:20150112-121106664Analog VLSI for auditory and vision signal processing
https://resolver.caltech.edu/CaltechAUTHORS:20141222-112010277
Year: 1988
DOI: 10.1109/IEDM.1988.32736
Various issues connected with the use of analog VLSI for auditory and vision signal processing are discussed. Particular attention is given to the impact of CMOS integrated-circuit technology and precision, reliability and noise considerations.https://resolver.caltech.edu/CaltechAUTHORS:20141222-112010277A silicon model of early visual processing
https://resolver.caltech.edu/CaltechAUTHORS:20141217-152336241
Year: 1988
DOI: 10.1016/0893-6080(88)90024-X
An analog model of the first stages of retinal processing has been constructed on a single silicon chip. Each photoreceptor computes the logarithm of the incident light intensity. A resistive network is used to compute a spatially smoothed version of the receptor outputs. An amplified difference between the receptor signals and their smoothed counterparts forms a second-order spatial filter. Measured outputs from an experimental 48 × 48 pixel array show many of the characteristics of the bipolar cells in vertebrate retina.https://resolver.caltech.edu/CaltechAUTHORS:20141217-152336241Winner-Take-All Networks of O(N) Complexity
https://resolver.caltech.edu/CaltechCSTR:1988.cs-tr-88-21
Year: 1988
DOI: 10.7907/32s8b-x9954
No abstract available.https://resolver.caltech.edu/CaltechCSTR:1988.cs-tr-88-21Cochlear Hydrodynamics Demystified
https://resolver.caltech.edu/CaltechCSTR:1988.cs-tr-88-04
Year: 1988
DOI: 10.7907/qysdt-52n82
Wave propagation in the mammalian cochlea (inner ear) is modeled as a unidirectional cascade of simple filters. The transfer functions of the low-order filter stages are completely determined by the wave-number vs. frequency solutions to the dispersion relations that describe the cochlea, which are in turn derived from twodimensional approximations to the fluid mechanics. Active undamping effects of the outer hair cells are easily included in the analysis and modeling, so that the results can be directly applied in the design of active adaptive cochlear models.https://resolver.caltech.edu/CaltechCSTR:1988.cs-tr-88-04Computing motion using analog and binary resistive networks
https://resolver.caltech.edu/CaltechAUTHORS:20141217-153250575
Year: 1988
DOI: 10.1109/2.31
The authors describe recent developments in the theory of early vision that led from the formulation of the motion problem as an ill-posed one to its solution by minimizing certain 'cost' functions. These cost or energy functions can be mapped onto simple analog and digital resistive networks. The optical flow is computed by injecting currents into resistive networks and recording the resulting stationary voltage distribution at each node. The authors believe that these networks, which they implemented in complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuits, represent plausible candidates for biological vision systems.https://resolver.caltech.edu/CaltechAUTHORS:20141217-153250575A CMOS VLSI cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20141222-151200537
Year: 1988
DOI: 10.1109/ICASSP.1988.197063
An engineered system that hears, such as a speech recognizer, can be designed by modeling the cochlea, or inner ear, and higher levels of the auditory nervous system. To be useful in such a system, a model
of the cochlea should incorporate a variety of known effects, such as an asymmetric lowpass/bandpass response at each output channel, a short ringing time, and active adaptation to a wide range of input signal
levels. An analog electronic cochlea has been built in CMOS VLSI technology using micropower techniques to achieve this goal of usefulness via realism. The key point of the model and circuit is that a cascade of simple, nearly linear, second-order filter stages with controllable
Q parameters suffices to capture the physics of the fluid-dynamic traveling-wave system in the cochlea, including the effects of adaptation and active gain involving the outer hair cells. Measurements on the test
chip suggest that the circuit matches both the theory and observations from real cochleas.https://resolver.caltech.edu/CaltechAUTHORS:20141222-151200537An analog electronic cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20141218-114000809
Year: 1988
DOI: 10.1109/29.1639
An analog electronic cochlea has been built in CMOS VLSI technology using micropower techniques. The key point of the model and circuit is that a cascade of simple, nearly linear, second-order filter stages with controllable Q parameters suffices to capture the physics of the fluid-dynamic traveling-wave system in the cochlea, including the effects of adaptation and active gain involving the outer hair cells. Measurements on the test chip suggest that the circuit matches both the theory and observations from real cochleas.https://resolver.caltech.edu/CaltechAUTHORS:20141218-114000809Analog VLSI and Neural Systems
https://resolver.caltech.edu/CaltechAUTHORS:20141215-163950138
Year: 1989
[No abstract]https://resolver.caltech.edu/CaltechAUTHORS:20141215-163950138Circuit Models of Sensory Transduction in the Cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20150918-160002977
Year: 1989
Nonlinear signal processing is an integral part of sensory transduction in
the nervous system. Sensory inputs are analog, continuous-time signals with a
large dynamic range, whereas central neurons encode information with limited
dynamic range and temporal specificity, using fixed-width, fixed-height pulses.
Sensory transduction uses nonlinear signal processing to reduce real-world input
to a neural representation, with a minimal loss of information.https://resolver.caltech.edu/CaltechAUTHORS:20150918-160002977Silicon Models of Neural Computation
https://resolver.caltech.edu/CaltechAUTHORS:20150927-224418112
Year: 1989
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150927-224418112An Electronic Photoreceptor Sensitive to Small Changes in Intensity
https://resolver.caltech.edu/CaltechAUTHORS:20141212-141111206
Year: 1989
We describe an electronic photoreceptor circuit that is sensitive to small changes in incident light intensity. The
sensitivity to changes in the intensity is achieved by feeding back to the input a filtered version of the output. The feedback loop includes a hysteretic element. The circuit
behaves in a manner reminiscent of the gain control properties and temporal responses of a variety of retinal cells, particularly retinal bipolar cells. We compare the thresholds for detection of intensity increments by a human and by the circuit. Both obey Weber's law and for both the temporal contrast sensitivities are nearly identical.https://resolver.caltech.edu/CaltechAUTHORS:20141212-141111206A silicon model of auditory localization
https://resolver.caltech.edu/CaltechAUTHORS:LAZnc89
Year: 1989
DOI: 10.1162/neco.1989.1.1.47
The barn owl accurately localizes sounds in the azimuthal plane, using interaural time difference as a cue. The time-coding pathway in the owl's brainstem encodes a neural map of azimuth, by processing interaural timing information. We have built a silicon model of the time-coding pathway of the owl. The integrated circuit models the structure as well as the function of the pathway; most subcircuits in the chip have an anatomical correlate. The chip computes all outputs in real time, using analog, continuous-time processing.https://resolver.caltech.edu/CaltechAUTHORS:LAZnc89Modeling Small Oscillating Biological Networks in Analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20141212-145236780
Year: 1989
We have used analog VLSI technology to model a class of small oscillating
biological neural circuits known as central pattern generators
(CPG). These circuits generate rhythmic patterns of activity
which drive locomotor behaviour in the animal. We have designed,
fabricated, and tested a model neuron circuit which relies on many
of the same mechanisms as a biological central pattern generator
neuron, such as delays and internal feedback. We show that this
neuron can be used to build several small circuits based on known
biological CPG circuits, and that these circuits produce patterns of
output which are very similar to the observed biological patterns.https://resolver.caltech.edu/CaltechAUTHORS:20141212-145236780Analog VLSI Models of Oscillatory Biological Neural Circuits
https://resolver.caltech.edu/CaltechAUTHORS:20150927-223445373
Year: 1989
We have used analog VLSI technology to model a class of biological neural circuits known as central pattern generators (CPGs). These circuits generate
rhythmic patterns of activity which drive motor behavior in animals. We have designed, fabricated, and tested a model neuron circuit that relies on many of the same mechanisms as a biological CPG neuron, and have shown
that this neuron can be used to build small models of known CPGs that produce patterns of output similar to the observed biological patterns.https://resolver.caltech.edu/CaltechAUTHORS:20150927-223445373Winner-Take-All Networks of O(N) Complexity
https://resolver.caltech.edu/CaltechAUTHORS:20141212-145244773
Year: 1989
We have designed, fabricated, and tested a series of compact CMOS integrated circuits that realize the winner-take-all function. These analog, continuous-time circuits use only O(n) of interconnect to perform this function. We have also modified the winner-take-all circuit, realizing a circuit that computes local nonlinear inhibition.https://resolver.caltech.edu/CaltechAUTHORS:20141212-145244773Neural computation in analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150120-164428118
Year: 1989
DOI: 10.1109/ACSSC.1989.1200737
Neural systems found in the brains of even very simple animals are amazingly effective at performing computations on information arising in the natural world. Neural structures expend less than a millionth of the power required by our most advanced digital
signal processing technology for a similar task. At the level of a single device, however, our silicon technology can much more closely approach the energy requirements of structures in the brain. The nervous system achieves its remarkable effectiveness by using the fundamental device physics to define its computational primitives. In addition, algorithmic structures that emphasize
spatial locality make best use of limited wiring resources. A deeper understanding of the design approach used by neural systems may make possible a new, and very powerful, engineering discipline.https://resolver.caltech.edu/CaltechAUTHORS:20150120-164428118Implementing neural architectures using analog VLSI circuits
https://resolver.caltech.edu/CaltechAUTHORS:20141218-114458819
Year: 1989
DOI: 10.1109/31.31311
Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.https://resolver.caltech.edu/CaltechAUTHORS:20141218-114458819Silicon Modeling of Pitch Perception
https://resolver.caltech.edu/CaltechAUTHORS:LAZpnas89
Year: 1989
DOI: 10.1073/pnas.86.23.9597
PMCID: PMC298545
We have designed and tested an integrated circuit that models human pitch perception. The chip receives as input a time-varying voltage corresponding to sound pressure at the ear and produces as output a map of perceived pitch. The chip is a physiological model; subcircuits on the chip correspond to known and proposed structures in the auditory system. Chip output approximates human performance in response to a variety of classical pitch-perception stimuli. The 125,000-transistor chip computes all outputs in real time by using analog continuous-time processing.https://resolver.caltech.edu/CaltechAUTHORS:LAZpnas89A Silicon Model of Auditory Localization
https://resolver.caltech.edu/CaltechAUTHORS:20150109-124214444
Year: 1990
The principles of organization of neural systems arose
from the combination of the performance requirements
for survival and the physics of neural elements. From
this perspective, the extraction of time-domain information
from auditory data is a challenging computation;
the system must detect changes in the data which
occur in tens of microseconds, using neurons which can
fire only once per several milliseconds. Neural
approaches to this problem succeed by closely coupling
algorithms and implementation, unlike standard engineering
practice, which aims to define algorithms that
are easily abstracted from hardware implementation.https://resolver.caltech.edu/CaltechAUTHORS:20150109-124214444An Analog VLSI Model of Adaptation in the Vestibulo-Ocular Reflex
https://resolver.caltech.edu/CaltechAUTHORS:20150130-161640003
Year: 1990
The vestibulo-ocular reflex (VOR) is the primary mechanism that controls the compensatory eye movements that stabilize retinal images during rapid head motion. The primary pathways of this system are feed-forward, with inputs from the semicircular canals and outputs to the oculomotor system. Since visual feedback is not used directly in the VOR computation, the system must exploit motor learning to perform correctly. Lisberger(1988) has proposed
a model for adapting the VOR gain using image-slip information from the retina. We have designed and tested analog very large-scale integrated (VLSI) circuitry that implements a simplified version of Lisberger's adaptive VOR model.https://resolver.caltech.edu/CaltechAUTHORS:20150130-161640003An Analog Electronic Cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20141222-163913984
Year: 1990
An engineered system that hears, such as a speech recognizer, can be designed by modeling the cochlea, or inner ear, and higher levels of the auditory nervous system. To be useful in such a system, a model of the cochlea should incorporate a variety of known effects,
such as an asymmetric low-pass/bandpass response at each output channel, a short ringing time, and active adaptation to a wide range of input signal levels. An analog electronic cochlea has been built in CMOS
VLSI technology using micropower techniques to achieve this goal of usefulness via realism. The key point of the model and circuit is that a cascade of simple, nearly linear, second-order filter stages with controllable
Q parameters suffices to capture the physics of the fluid-dynamic traveling-wave system in the cochlea, including the effects of adaptation and active gain involving the outer hair cells. Measurements
on the test chip suggest that the circuit matches both the theory and observations from real cochleas.https://resolver.caltech.edu/CaltechAUTHORS:20141222-163913984VLSI Implementation of Neural Networks
https://resolver.caltech.edu/CaltechAUTHORS:20150109-122323757
Year: 1990
The recent resurgence of interest in neural networks
(NNs) has resulted in the application of NNs to a
variety of problem domains. The initial results show
great promise, which in tum is motivating research in
appropriate implementation technologies. Several approaches
are now being explored; at one extreme of
the spectrum is algorithmic research for software running
on a conventional computer, whereas at the
other extreme researchers are exploring radically new
computational structures, such as optical computing.
A more conservative approach relies on adapting the
existing silicon-based CMOS VLSI (complementary
metal oxide semiconductor, very large scale integration)
technology to the unique needs of NN
computation.https://resolver.caltech.edu/CaltechAUTHORS:20150109-122323757Auditory Processing Using Analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150112-144142710
Year: 1990
The architectures of animal nervous systems are shaped by evolution and
carried in the genetic code. The essential quality of such an architecture is
that it must learn from the environment in which the animal lives. The single
common element of learning is the time coincidence in the arrival of nerve
impulses. The arrival of one impulse or burst of impulses closely followed
by another is taken by the nervous system as evidence for a cause-and-effect
relationship between the two. The temporal structure of auditory stimuli
encodes far more information than standard engineering methods have ever
been able to extract. The fact that animal nervous systems can extract this
information leads to the conclusion that heretofore unexplored computational
paradigms are involved. The design of large-scale integrated circuits
employing a substantial fraction of analog processing is a promising
approach to this class of problems.https://resolver.caltech.edu/CaltechAUTHORS:20150112-144142710A Novel Associative Memory Implemented Using Collective Computation
https://resolver.caltech.edu/CaltechAUTHORS:20141223-104942966
Year: 1990
A radically new type of associative memory, the ASSOCMEM, has been implemented in VLSI and tested. Analog circuit techniques are used to construct a network that evolves towards fully restored (digital) fixed-points that are the memories of the system. Association occurs
on the whole source word, each bit of which may assume a continuous analog value. The network does not require the distinction of a search key from a data field in either the source or target words. A key may be dynamically defined by differentially weighting any subset of the source
word. The key need not be exact; the system will evolve to the closest memory. In the case when the key is the whole input word, the system may be thought of as performing error correction.https://resolver.caltech.edu/CaltechAUTHORS:20141223-104942966Fundamental transition in the electronic nature of solids
https://resolver.caltech.edu/CaltechAUTHORS:20210127-142447762
Year: 1990
DOI: 10.1007/978-94-009-0657-0_10
The fundamental electronic properties of non- metallic, inorganic, crystalline solids depend in a natural manner on the character of the chemical bond which is developed between constituent atoms. For example, the familiar Group-IV semiconductors are totally covalent and exhibit characteristics which are qualitatively different from highly ionic materials, such as the alkali halides. However, many materials of fundamental and practical importance are intermediate between these two extremes; it is not immediately evident how their properties may be treated. We will demonstrate here that if crystalline solids are ordered by some measure of their bond ionicity, then one finds striking evidence for a universal and surprisingly abrupt transition in many electronic properties associated with the quantum mechanical valence state. This transition divides crystalline solids into two well-defined classes: "covalent" and "ionic." Within each class there is a unifying character to the observed properties.https://resolver.caltech.edu/CaltechAUTHORS:20210127-142447762Machines Will Understand the World
https://resolver.caltech.edu/CaltechAUTHORS:20141212-163723123
Year: 1990
[No abstract]https://resolver.caltech.edu/CaltechAUTHORS:20141212-163723123A neuron-based pulse servo for motion control
https://resolver.caltech.edu/CaltechAUTHORS:20141222-120754146
Year: 1990
DOI: 10.1109/ROBOT.1990.126254
Sensory control based on biological computational
paradigms can be implemented using low-power
analog very large-scale integrated circuitry. We describe
a design frame and a set of circuit elements with which
generic motor controllers can be implemented. We then
embed a simple proportional-derivative motor controller
in the design frame, and describe its performance advantages
over a more traditional controller. We also discuss
the merits of biologically inspired systems used in applications related to robotics.https://resolver.caltech.edu/CaltechAUTHORS:20141222-120754146Neuromorphic electronic systems
https://resolver.caltech.edu/CaltechAUTHORS:20141222-113217405
Year: 1990
DOI: 10.1109/5.58356
Biological in formation-processing systems operate on completely different principles from those with which most engineers are familiar. For many problems, particularly those in which the input data are ill-conditioned and the computation can be specified in a relative manner, biological solutions are many orders of magnitude more effective than those we have been able to implement
using digital methods. This advantage can be attributed principally to the use of elementary physical phenomena as computational primitives, and to the representation of information by the relative values of analog signals, rather than by the absolute values of digital signals. This approach requires adaptive techniques to
mitigate the effects of component differences. This kind of adaptation leads naturally to systems that learn about their environment. Large-scale adaptive analog systems are more robust to component degradation and failure than are more conventional systems, and they use far less power. For this reason, adaptive analog technology can be expected to utilize the full potential of wafer-scale silicon fabrication.https://resolver.caltech.edu/CaltechAUTHORS:20141222-113217405A simple neuron servo
https://resolver.caltech.edu/CaltechAUTHORS:20141222-120307757
Year: 1991
DOI: 10.1109/72.80335
This paper describes a simple servo controller build from
components having neuronlike features. Experimental results illustrate
the properties of the system, and a comparison is made with conventional
controllers.https://resolver.caltech.edu/CaltechAUTHORS:20141222-120307757Analog VLSI model of binaural hearing
https://resolver.caltech.edu/CaltechAUTHORS:20141222-115251890
Year: 1991
DOI: 10.1109/72.80333
The stereausis model of biological auditory processing was
proposed as a representation that encodes both binaural and spectral
information in a unified framework. We describe a working analog
VLSI chip that implements this model of early auditory processing in
the brain. The chip is a 100 000-transistor integrated circuit that computes
the stereausis representation in real time, using continuous-time
analog processing. The chip receives two audio inputs, representing
sound entering the two ears, computes the stereausis representation,
and generates output signals that can directly drive a color CRT display.https://resolver.caltech.edu/CaltechAUTHORS:20141222-115251890The Silicon Retina
https://resolver.caltech.edu/CaltechAUTHORS:20150112-144735576
Year: 1991
A chip based on the neural architecture
of the eye proves a new, more powerful
way of doing computations.https://resolver.caltech.edu/CaltechAUTHORS:20150112-144735576Scanners for visualizing activity of analog VLSI circuitry
https://resolver.caltech.edu/CaltechAUTHORS:20141222-162320871
Year: 1991
DOI: 10.1007/BF00161303
This paper tutorially describes mixed digital-analog serial multiplexers (scanners) that we use to visualize the activity of one- and two-dimensional arrays of analog VLSI elements. These scanners range from simple one-dimensional devices designed to scan a one-dimensional array onto an oscilloscope, to complete video scanners with integrated sync and blank computation and on-chip video amplifiers. We discuss practical details of design and performance, and we give a source for example scanner layout.https://resolver.caltech.edu/CaltechAUTHORS:20141222-162320871Time-derivative adaptive silicon photoreceptor array
https://resolver.caltech.edu/CaltechAUTHORS:20150227-114653482
Year: 1991
DOI: 10.1117/12.49323
We designed and tested a two-dimensional silicon receptor array constructed from pixels that temporally high-pass filter the incident image. There are no surround interactions in the array; all pixels operate independently except for their correlation due to the input image. The high- pass output signal is computed by sampling the output of an adaptive, high-gain, logarithmic photoreceptor during the scanout of the array. After a pixel is sampled, the output of the pixel is reset to a fixed value. An interesting capacitive coupling mechanism results in a controllable high-pass filtering operation. The resulting array has very low offsets. The computation that the array performs may be useful for time-domain image processing, for example, motion computation.https://resolver.caltech.edu/CaltechAUTHORS:20150227-114653482An introduction to silicon neural analogs
https://resolver.caltech.edu/CaltechAUTHORS:20150915-135808440
Year: 1992
DOI: 10.1016/1044-5765(92)90036-2
Synthetic neural systems that operate in real time have
been fabricated using analog complementary metal-oxide-
semiconductor (CMOS) very large scale integration (VLSI)
technology. The analog silicon system surpasses the
computational power of a general-purpose digital computer
because, from device physics to circuit architecture, its form parallels the functional organization of the neural system. Because the CMOS circuit represents neural processing directly in hardware, it is not simply a simulation tool but rather an analog neural system that is embedded in, and interacts with, the real world.https://resolver.caltech.edu/CaltechAUTHORS:20150915-135808440Improved implementation of the silicon cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20141222-121340994
Year: 1992
DOI: 10.1109/4.133156
The original "analog electronic cochlea" of Lyon
and Mead (1988) used a cascade of second-order filter sections in subthreshold analog VLSI to implement a low-power, real-time model of early auditory processing. Experience with many silicon-cochlea chips has allowed the identification of a number of important design issues, namely dynamic range, stability,
device mismatch, and compactness. In this paper, the original design is discussed in light of these issues, and circuit and layout techniques are described which significantly improve its performance, robustness, and efficiency. Measurements from test chips verify the improved performance.https://resolver.caltech.edu/CaltechAUTHORS:20141222-121340994Neural computing challenges the status quo
https://resolver.caltech.edu/CaltechAUTHORS:20141223-111358271
Year: 1992
For this Special Report on Future
Computing, Computer Design interviewed
Carver Mead, an expert on the
subject of neural computing. Professor
Mead is the Gordon and Betty Moore
Professor of Computer Science at the
California Institute of Technology, where
he has taught for 20 years. He's also a
co-founder and chairman of Synaptics,
a company that develops neural network
technology Mead has pioneered
in many areas of electronics, from the invention
of the MESFET to silicon compilers
and, recently, VLSI analog neural
systems.https://resolver.caltech.edu/CaltechAUTHORS:20141223-111358271A Silicon Model of Early Visual Processing
https://resolver.caltech.edu/CaltechAUTHORS:20141223-110732666
Year: 1993
Many of the most striking phenomena known from perceptual
psychology are a direct result of the first levels of
neural processing. In the visual systems of higher animals,
the well-known center-surround response to local stimuli is
responsible for some of the strongest visual illusions. For
example, Mach bands, the Hermann-Hering grid illusion,
and the Craik-O'Brian-Comsweet illusion can all be traced
to simple inhibitory interactions between elements of the
retina (Ratliff 1965). The high degree to which a perceived
image is independent of the absolute illumination
level can be viewed as a property of the mechanism by
which incident light is transduced into an electrical signal.
We present a model of the first stages of retinal processing
in which these phenomena are viewed as natural
by-products of the mechanism by which the system
adapts to a wide range of viewing conditions. Our retinal
model is implemented as a single silicon chip, which contains
integrated photoreceptors and processing elements;
this chip generates, in real time, outputs that correspond
directly to signals observed in the corresponding levels of
biological retinas.https://resolver.caltech.edu/CaltechAUTHORS:20141223-110732666White noise in MOS transistors and resistors
https://resolver.caltech.edu/CaltechAUTHORS:20141222-153004031
Year: 1993
DOI: 10.1109/101.261888
The theoretical and experimental results for white noise in the low-power subthreshold region of operation of an MOS transistor are discussed. It is shown that the measurements are consistent with the theoretical predictions. Measurements of noise in photoreceptors-circuits containing a photodiode and an MOS transistor-that are consistent with theory are reported. The photoreceptor noise measurements illustrate the intimate connection of the equipartition theorem of statistical mechanics with noise calculations.https://resolver.caltech.edu/CaltechAUTHORS:20141222-153004031Adaptive Photoreceptor with Wide Dynamic Range
https://resolver.caltech.edu/CaltechAUTHORS:20150113-105738115
Year: 1994
DOI: 10.1109/ISCAS.1994.409266
We describe a photoreceptor circuit that can be used in massively parallel analog VLSI silicon chips, in conjunction
with other local circuits, to perform initial analog visual
information processing. The receptor provides a continuous-time output that has low gain for static signals (including circuit mismatches), and high gain for transient signals that are centered around the adaptation point. The response is logarithmic, which makes the response to a fixed image contrast invariant to absolute light intensity. The 5-transistor receptor can be fabricated in an area of about 70 μm by 70 μm in a 2-μm single-poly CMOS technology. It has a dynamic range of 1-2 decades at a single adaptation level, and a total dynamic range of more than 6 decades. Several technical improvements in the circuit yield an additional 1-2 decades dynamic range over previous designs without sacrificing signal quality. The lower limit of the dynamic range, defined arbitrarily as the illuminance at which the bandwidth of the
receptor is 60 Hz, is at approximately 1 lux, which is the border between rod and cone vision and also the limit of current consumer video cameras. The receptor uses an adaptive element that is resistant to excess minority carrier diffusion. The continuous and logarithmic transduction process makes the bandwidth scale with intensity. As a result, the total A.C.
RMS receptor noise is constant, independent of intensity.
The spectral density of the noise is within a factor of two of pure photon shot noise and varies inversely with intensity. The connection between shot and thermal noise in a system governed by Boltzman statistics is beautifully illustrated.https://resolver.caltech.edu/CaltechAUTHORS:20150113-105738115Continuous-time adaptive delay system
https://resolver.caltech.edu/CaltechAUTHORS:20150113-105207012
Year: 1994
DOI: 10.1109/ISCAS.1994.409212
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 μm CMOS technology are in agreement with the analysishttps://resolver.caltech.edu/CaltechAUTHORS:20150113-105207012Scaling of MOS technology to submicrometer feature sizes
https://resolver.caltech.edu/CaltechAUTHORS:20150109-125350741
Year: 1994
DOI: 10.1007/BF02407107
Industries based on MOS technology now play a prominent role in the developed and the developing
world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely
that the course of technological development depends more on the capability of MOS technology than on any other
technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS
fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the
attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level.
This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict
the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the
minimum size approaches physical limits.https://resolver.caltech.edu/CaltechAUTHORS:20150109-125350741Scaling of MOS Technology to Submicrometer Feature Sizes
https://resolver.caltech.edu/CaltechAUTHORS:20141222-161742429
Year: 1994
DOI: 10.1007/BF01250732
Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.https://resolver.caltech.edu/CaltechAUTHORS:20141222-161742429A Silicon Axon
https://resolver.caltech.edu/CaltechAUTHORS:20150305-152221206
Year: 1995
We present a silicon model of an axon which shows promise as a building block for pulse-based neural computations involving correlations of pulses across both space and time. The circuit shares a number of features with its biological counterpart including an
excitation threshold, a brief refractory period after pulse completion, pulse amplitude restoration, and pulse width restoration. We provide a simple explanation of circuit operation and present data from a chip fabricated in a standard 2μm CMOS process through the MOS Implementation Service (MOSIS). We emphasize the necessity
of the restoration of the width of the pulse in time for stable propagation in axons.https://resolver.caltech.edu/CaltechAUTHORS:20150305-152221206Single Transistor Learning Synapses
https://resolver.caltech.edu/CaltechAUTHORS:20150305-153222850
Year: 1995
We describe single-transistor silicon synapses that compute, learn, and provide non-volatile memory retention. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and the weight value, and update the weight value according to a Hebbian or a backpropagation learning rule. Memory is accomplished via charge storage on polysilicon
floating gates, providing long-term retention without refresh. The synapses efficiently use the physics of silicon to perform weight updates; the weight value is increased using tunneling and the weight
value decreases using hot electron injection. The small size and low power operation of single transistor synapses allows the development of dense synaptic arrays. We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. When the steady state source current is used as
the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current. The synaptic array was fabricated in the standard 2μm double - poly, analog process available from MOSIS.https://resolver.caltech.edu/CaltechAUTHORS:20150305-153222850Neuromorphic analogue VLSI
https://resolver.caltech.edu/CaltechAUTHORS:DOUarn95
Year: 1995
DOI: 10.1146/annurev.ne.18.030195.001351
Neuromorphic systems emulate the organization and function of nervous systems. They are usually composed of analogue electronic circuits that are fabricated in the complementary metal-oxide-semiconductor (CMOS) medium using very large-scale integration (VLSI) technology. However, these neuromorphic systems are not another kind of digital computer in which abstract neural networks are simulated symbolically in terms of their mathematical behavior. Instead, they directly embody, in the physics of their CMOS circuits, analogues of the physical processes that underlie the computations of neural systems. The significance of neuromorphic systems is that they offer a method of exploring neural computation in a medium whose physical behavior is analogous to that of biological nervous systems and that operates in real time irrespective of size. The implications of this approach are both scientific and practical. The study of neuromorphic systems provides a bridge between levels of understanding. For example, it provides a link between the physical processes of neurons and their computational significance. In addition, the synthesis of neuromorphic systems transposes our knowledge of neuroscience into practical devices that can interact directly with the real world in the same way that biological nervous systems do.https://resolver.caltech.edu/CaltechAUTHORS:DOUarn95A High-Resolution Non-Volatile Analog Memory Cell
https://resolver.caltech.edu/CaltechAUTHORS:20150113-150432993
Year: 1995
DOI: 10.1109/ISCAS.1995.523872
A 3-transistor non-volatile analog storage cell with 14 bits effective resolution and rail-to-rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hot-electron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feedback control, errors due to oxide mismatch or trapping can be nearly eliminated, Small size and low power consumption make the cell especially attractive for use in analog neural networks. The cell is fabricated in a 2 μm n-well silicon Bi-CMOS process available from MOSIS.https://resolver.caltech.edu/CaltechAUTHORS:20150113-150432993Single transistor learning synapse with long term storage
https://resolver.caltech.edu/CaltechAUTHORS:20150113-122333554
Year: 1995
DOI: 10.1109/ISCAS.1995.523729
We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectivity for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current.https://resolver.caltech.edu/CaltechAUTHORS:20150113-122333554A νMOS soft-maximum current mirror
https://resolver.caltech.edu/CaltechAUTHORS:20150113-151535084
Year: 1995
DOI: 10.1109/ISCAS.1995.523876
In this paper, we describe a novel circuit consisting of N+1 MOS transistors and a single floating gate which computes a soft maximum of N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage swing and an interesting feedback mechanism which causes its output impedance to be comparable to that of a normal MOS transistor despite the fact that the output device is a floating-gate transistor.https://resolver.caltech.edu/CaltechAUTHORS:20150113-151535084New approach to data-path synthesis
https://resolver.caltech.edu/CaltechAUTHORS:20150313-134029205
Year: 1995
Data paths are collections of arithmetic elements, buses, registers and multiplexers that usually
account for roughly 80 percent of the area of a complex chip. Unfortunately, gate-level synthesis does not work
well for these elements. Data-path synthesis solves this problem by keeping the design at a conceptually higher
level than gate-level synthesis, thus allowing much larger designs.https://resolver.caltech.edu/CaltechAUTHORS:20150313-134029205Simulation of a long term memory device with a full bandstructure Monte Carlo approach
https://resolver.caltech.edu/CaltechAUTHORS:20150112-160605437
Year: 1995
DOI: 10.1109/55.400738
Simulations of charging characteristics of a long
term memory device, based on a floating gate structure, are
presented. The analysis requires the inclusion of hot electron effects
and a detailed account of the semiconductor bandstructure,
because device operation is based on the injection of electrons
into the gate oxide high above the silicon conduction band edge.
We have developed a Monte Carlo simulator based on a full
bandstructure approach which accurately accounts for the high
energy tail of the electron distribution function. For practical
simulation of the prototype structure, with 3.0-pm source-drain
separation, the simulator is used as a post-processor on the
potential profile obtained from a PISCES IIB drift-diffusion
solution. The computations are in quantitative agreement with
experimental results for the gate injection current, measured at
fixed drain and gate biases.https://resolver.caltech.edu/CaltechAUTHORS:20150112-160605437An analog VLSI cochlea with new transconductance amplifiers and nonlinear gain control
https://resolver.caltech.edu/CaltechAUTHORS:20150113-155313873
Year: 1996
DOI: 10.1109/ISCAS.1996.541591
We show data from a working 45-stage analog VLSI cochlea, built on a 2.2 mm×2.2 mm tiny chip. The novel architectural features in this cochlea are: (1) The use of a wide-linear-range low-noise subthreshold transconductance amplifier. (2) The use of "fuse-like" nonlinear positive-feedback amplification in the second-order cochlear filter. Several new circuit techniques used in the design are described here. The fuse nonlinearity shuts off the positive-feedback amplification at large signal levels instead of merely saturating it, like in prior designs, and leads to increased adaptation and improved large-signal stability in the filter. The fuse filter implements a functional model of gain control due to outer hair cells in the biological cochlea. We present data for travelling-wave patterns in our silicon cochlea that reproduce linear and nonlinear effects in the biological cochlea.https://resolver.caltech.edu/CaltechAUTHORS:20150113-155313873Translinear Circuits Using Subthreshold Floating-Gate MOS Transistors
https://resolver.caltech.edu/CaltechAUTHORS:20141222-163230369
Year: 1996
DOI: 10.1007/BF00166412
We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2μm double-poly p-well process through MOSIS.https://resolver.caltech.edu/CaltechAUTHORS:20141222-163230369An autozeroing amplifier using PFET hot-electron injection
https://resolver.caltech.edu/CaltechAUTHORS:20150113-155800936
Year: 1996
DOI: 10.1109/ISCAS.1996.541599
We have developed an amplifier which removes its "off-set" as a natural part of its operation by modifying the charge on a floating gate. The charge on the floating gate is adapted by a combination of electron tunneling and hot-electron injection, resulting in a nonlinear high-pass filter with a cutoff frequency less than 1 Hz. We show experimental data from this autozeroing amplifier for various input waveforms, and an analytical model which fits the output waveforms. This autozeroing amplifier is a single-input case of a continuous learning circuit.https://resolver.caltech.edu/CaltechAUTHORS:20150113-155800936The matching of small capacitors for analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150113-154605832
Year: 1996
DOI: 10.1109/ISCAS.1996.539873
The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 μm×6 μm to 20 μm×20 μm fabricated in a standard 2 μm double-poly CMOS process available through MOSIS. For a size of 6 μm×6 μm, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 μm×20 μm size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching.https://resolver.caltech.edu/CaltechAUTHORS:20150113-154605832Nonvolatile correction of Q-offsets and instabilities in cochlear filters
https://resolver.caltech.edu/CaltechAUTHORS:20150113-160204726
Year: 1996
DOI: 10.1109/ISCAS.1996.541600
We present a feedback circuit that performs nonvolatile correction of instabilities and resonant-gain offsets (Q-offsets) in individual cochlear filters. The subthreshold CMOS circuit adapts using analog floating-gate technology. We present experimental data from a working chip that illustrates the performance of the circuit. We discuss how to extend our work to do very long-term gain control in the silicon cochlea. Positive-feedback circuits, such as our cochlear filters, are very sensitive to parameter variations. This potential problem becomes an advantage in our corrective feedback loop where the hypersensitivity behaves merely like high loop gain.https://resolver.caltech.edu/CaltechAUTHORS:20150113-160204726Continuous-time adaptive delay system
https://resolver.caltech.edu/CaltechAUTHORS:20150113-160926108
Year: 1996
DOI: 10.1109/82.544027
We have developed a direction-selective system that has a row of pixels with photodiodes as the front-end. The output of each photodiode is converted to a digital signal, which is then fed to an adaptive-delay block within each pixel. The adaptive block adjusts an internal delay such that the delay matches the phase offset between the rising edges of this digital signal and the corresponding digital signal from the neighboring pixel. The system does this delay matching by using a dynamic current source to adapt the bias voltage that controls the delay. The adaptive-delay block is similar to a digital charge-pump phase-lock loop (PLL). It differs from conventional PLL's however, both in its compact size and its lack of a system clock. It also has a fast pull-in time during the locking of the signal. Since our application does not require low jitter, we have not introduced a phase offset in the comparator as is typically done in PLLs. The transistors here are operated In subthreshold. A stability analysis of the feedback system leads to simple stability and convergence constraints. Experimental results from circuits fabricated in 2 μm CMOS technology show that the circuit can lock over 5 decades of frequency.https://resolver.caltech.edu/CaltechAUTHORS:20150113-160926108A single-transistor silicon synapse
https://resolver.caltech.edu/CaltechAUTHORS:20150113-160500726
Year: 1996
DOI: 10.1109/16.543035
We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory-update rule from the physics of the tunneling and injection processes, and have investigated synapse learning in a prototype array. Unlike conventional EEPROM devices, the synapse allows simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. The synapse is small, and typically is operated at subthreshold current levels; it will permit the development of dense, low-power silicon learning systems.https://resolver.caltech.edu/CaltechAUTHORS:20150113-160500726Scaling of MOS technology
https://resolver.caltech.edu/CaltechAUTHORS:20150127-164258678
Year: 1996
DOI: 10.1109/40.546564
The MOS transistor is the workhorse of modern microelectronics. Reducing the feature size of CMOS fabrication processes has been the primary method by which ever-increasing computation could proceed at ever-decreasing
cost and power consumption. How does this scaling affect
device performance? Are there fundamental physical limits
to how small die MOS device, as we know it today, can
be scaled?https://resolver.caltech.edu/CaltechAUTHORS:20150127-164258678A Complementary Pair of Four-Terminal Silicon Synapses
https://resolver.caltech.edu/CaltechAUTHORS:20150127-165006071
Year: 1997
DOI: 10.1023/A:1008244314595
We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling
permit bidirectional memory updates. Because these updates depend on both the stored memory value and the
transistor terminal voltages, the synapses can implement a learning function. We have derived a memory-update
rule for both devices, and have shown that the synapse learning follows a simple power law. Unlike conventional
EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore
compute both the array output, and local memory updates, in parallel. We have fabricated prototype synaptic
arrays; because the tunneling and injection processes are exponential in the transistor terminal voltages, the write
and erase isolation between array synapses is better than 0.01%. The synapses are small, and typically are operated
at subthreshold current levels; they will permit the development of dense, low-power silicon learning systems.https://resolver.caltech.edu/CaltechAUTHORS:20150127-165006071A Low-Power Wide-Linear-Range Transconductance Amplifier
https://resolver.caltech.edu/CaltechAUTHORS:20150128-101534368
Year: 1997
DOI: 10.1023/A:1008292213687
The linear range of approximately ±75mV of traditional subthreshold transconductance amplifiers is too small for certain applications—for example, for filters in electronic cochleas, where it is desirable to handle loud sounds without distortion and to have a large dynamic range.We describe a transconductance amplifier designed for low-power(< 1 µW) subthreshold operation with a wide input linear range. We obtain wide linear range by widening the tanh, or decreasing the ratio of transconductance to bias current,by a combination of four techniques. First, the well terminals of the input differential-pair transistors are used as the amplifier inputs. Then, feedback techniques known as source degeneration( a common technique) and gate degeneration (a new technique) provide further improvements. Finally, a novel bump-linearization technique extends the linear range even further. We present signal-flow diagrams for speedy analysis of such circuit techniques. Our transconductance reduction is achieved in a compact 13-transistor circuit without degrading other characteristics such as dc-input operating range. In a standard 2 µm process,we were able to obtain a linear range of ±1.7V.Using our wide-linear-range amplifier and a capacitor, we construct a follower–integrator with an experimental dynamic range of 65 dB. We show that, if the amplifier's noise is predominantly thermal, then an increase in its linear range increases the follower–integrator's dynamic range. If the amplifier's noise is predominantly 1/f,then an increase in its linear range has no effect on the follower–integrator's dynamic range. To preserve follower–integrator bandwidth,power consumption increases proportionately with an increase in the amplifier's linear range. We also present data for changes in the subthreshold exponential parameter with current level and with gate-to-bulk voltage that should be of interest to all low-power designers. We have described the use of our amplifier in a silicon cochlea.https://resolver.caltech.edu/CaltechAUTHORS:20150128-101534368A High Resolution CMOS Imager With Active Pixel Using Capacitively Coupled Bipolar Operation
https://resolver.caltech.edu/CaltechAUTHORS:20150113-161240691
Year: 1997
DOI: 10.1109/VTSA.1997.614727
The active pixel sensor technology promises high
performance than conventional CCD imagers. This paper
reports a new high resolution CMOS imager with one
transistor active pixel sensing based on capacitor-coupled
bipolar action. The base capacitor is pulsed negatively for
image integration and positively for image sensing. The pixel size is 5.9um x 5.9um (on 0.8um design rule). The prototype imager has an array of 480 x 640 and operating at 5v Vcc. This active pixel structure is promising for future high-performance and high-density imagers in the information highway era.https://resolver.caltech.edu/CaltechAUTHORS:20150113-161240691Collective electrodynamics I
https://resolver.caltech.edu/CaltechAUTHORS:MEApnas97
Year: 1997
PMCID: PMC20992
Standard results of electromagnetic theory are derived from the direct interaction of macroscopic quantum systems; the only assumptions used are the Einstein-deBroglie relations, the discrete nature of charge, the Green's function for the vector potential, and the continuity of the wave function. No reference is needed to Maxwell's equations or to traditional quantum formalism. Correspondence limits based on classical mechanics are shown to be inappropriate.https://resolver.caltech.edu/CaltechAUTHORS:MEApnas97A floating-gate MOS learning array with locally computed weight updates
https://resolver.caltech.edu/CaltechAUTHORS:20150113-162250820
Year: 1997
DOI: 10.1109/16.644652
We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 μs, whereas the weight normalization takes minutes to hours.https://resolver.caltech.edu/CaltechAUTHORS:20150113-162250820A Low-Power Wide-Linear-Range Transconductive Amplifier
https://resolver.caltech.edu/CaltechAUTHORS:20150112-105932717
Year: 1998
In the past few years, engineers have improved the linearity of MOS transconductor
circuits 12, 5, 10, 11, 19, 20, 26, 28, 29, 32]. These advances have been primarily
in the area of above-threshold, high-power, high-frequency, continuous-time
filters. Although it is possible to implement auditory filters (20Hz- 20khz)
with these techniques, it is inefficient to do so. The transconductance and current
levels in above-threshold operation are so high that large capacitances or
transistors with very low W / L are required to create low-frequency poles, and
area and power are wasted. In addition, it is difficult to span 3 orders of magnitude
of transconductance with a square law, unless we use transistors with
ungainly aspect ratios. However, it is easy to obtain a wide linear range above
threshold.https://resolver.caltech.edu/CaltechAUTHORS:20150112-105932717Impact Ionization and Hot-Electron Injection Derived Consistently from Boltzmann Transport
https://resolver.caltech.edu/CaltechAUTHORS:HASvd98
Year: 1998
DOI: 10.1155/1998/73698
We develop a quantitative model of the impact-ionizationand hot-electron–injection processes in MOS devices from first principles. We begin by modeling hot-electron transport in the drain-to-channel depletion region using the spatially varying Boltzmann transport equation, and we analytically find a self consistent distribution function in a two step process. From the electron distribution function, we calculate the probabilities of impact ionization and hot-electron injection as functions of channel current, drain voltage, and floating-gate voltage. We compare our analytical model results to measurements in long-channel devices. The model simultaneously fits both the hot-electron- injection and impact-ionization data. These analytical results yield an energydependent impact-ionization collision rate that is consistent with numerically calculated collision rates reported in the literature.https://resolver.caltech.edu/CaltechAUTHORS:HASvd98Floating-Gate MOS Synapse Transistors
https://resolver.caltech.edu/CaltechAUTHORS:20150109-144208064
Year: 1998
DOI: 10.1007/978-0-585-28001-1_14
Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile
analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices,
such as EEPROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate
transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si0_2, these devices have not seen wide use as memory elements in silicon learning systems.https://resolver.caltech.edu/CaltechAUTHORS:20150109-144208064A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20150112-105156628
Year: 1998
In this paper we describe a cochlea that attains a dynamic range of 6ldB at the BF of a typical cochlear stage by using four techniques:
1. The previously described WLR
2. A low-noise second-order filter topology
3. Dynamic gain control (AGC)
4. The architecture of overlapping cochlear cascades
In addition, we use three techniques that ensure the presence of a robust infrastructure
in the cochlea:
l. Automatic offset-compensation circuitry in each cochlear filter prevents offset accumulation along the cochlea.
2. Cascode circuitry in the WLRs increase the latter's DC gain, and prevent low-frequency signal attenuation in the cochlea.
3. Translinear bipolar biasing circuits provide Qs that are approximately invariant with corner frequency, and allow better matching. Bipolar biasing circuits were first used in cochlear designs by [32].
We shall discuss all of these preceding techniques in this paper.https://resolver.caltech.edu/CaltechAUTHORS:20150112-105156628A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20150127-164613163
Year: 1998
DOI: 10.1023/A:1008218308069
Low-power wide-dynamic-range systems are extremely hard to build. The biological cochlea is one of the most awesome examples of such a system: It can sense sounds over 12 orders of magnitude in intensity, with an
estimated power dissipation of only a few tens of microwatts. In this paper, we describe an analog electronic
cochlea that processes sounds over 6 orders of magnitude in intensity, and that dissipates 0.5mW. This 117-stage,
100 Hz to 10 KHz cochlea has the widest dynamic range of any artificial cochlea built to date. The wide dynamic
range is attained through the use of a wide-linear-range transconductance amplifier, of a low-noise filter topology,
of dynamic gain control (AGC) at each cochlear stage, and of an architecture that we refer to as overlapping
cochlear cascades. The operation of the cochlea is made robust through the use of automatic offset-compensation
circuitry. A BiCMOS circuit approach helps us to attain nearly scale-invariant behavior and good matching at all
frequencies. The synthesis and analysis of our artificial cochlea yields insight into why the human cochlea uses an
active traveling-wave mechanism to sense sounds, instead of using bandpass filters. The low power, wide dynamic
range, and biological realism make our cochlea well suited as a front end for cochlear implants.https://resolver.caltech.edu/CaltechAUTHORS:20150127-164613163Active-Pixel Sensors With "Winner-Take-All" Mode
https://resolver.caltech.edu/CaltechAUTHORS:20150915-132810466
Year: 1998
Circuits to generate the intensity
reading and the coordinates of the
brightest pixel in each image would be
added to imaging photodetector arrays
of the active-pixel-sensor (APS) type,
according to a proposal. For a given
APS, the additional circuitry for locating
the brightest pixel would be installed
at the periphery of the basic
APS circuit. The additional circuitry
would thus not degrade the original
optical properties or interfere with the
original electronic functions of the
APS. The APS could be operated in its
normal image-readout mode or, optionally,
it could be operated with the
additional circuitry in the brightest-pixel
mode. Potential applications
could include star tracking or fast
tracking of a moving laser-beam spot in
laser communication system.https://resolver.caltech.edu/CaltechAUTHORS:20150915-132810466Feynman as a colleague
https://resolver.caltech.edu/CaltechAUTHORS:20150109-111939447
Year: 1999
Feynman and I both arrived at Caltech in 1952 - he as a new professor of physics, and I as a freshman undergraduate. My passionate interest was electronics, and I avidly consumed any material I could find on the subject: courses, seminars,
books, etc. As a consequence, I was dragged through several versions of standard electromagnetic theory: E and B, D and H, curls of curls, the whole nine yards.
The only bright light in the subject was the vector potential, to which I was always attracted because, somehow, it made sense to me. It seemed a shame that the
courses I attended didn't make more use of it. In my junior year, I took a course in mathematical physics from Feynman - what a treat. This man could think conceptually about physics, not just regurgitate dry formalism. After one quarter of Feynman, the class was spoiled for any other professor. But when we looked at the registration form for the next quarter, we found Feynman as teaching high-energy
physics, instead of our course. Bad luck! When our first class met, however, here came Feynman. "So you're not teaching high-energy physics?" I asked. "No" he replied, "low-energy mathematics." Feynman liked the vector potential too; for him it was the link between electromagnetism and quantum mechanics. As he put it
"In the general theory of quantum electrodynamics, one takes the vector and scalar potentials as fundamental quantities in a set of equations that replace the Maxwell
equations." I learned enough about it from him to know that, some day, I wanted to do all of electromagnetic theory that way.https://resolver.caltech.edu/CaltechAUTHORS:20150109-111939447Collective Electrodynamics I
https://resolver.caltech.edu/CaltechAUTHORS:20150109-113726556
Year: 1999
Standard results of electromagnetic theory are derived from the direct interaction of macroscopic quantum systems; the only assumptions used are the Einstein-deBroglie
relations, the discrete nature of charge, the Green's function for the vector potential, and the continuity of the wave function. No reference is needed to
Maxwell's equations or to traditional quantum formalism. Correspondence limits based on classical mechanics are shown to be inappropriate.https://resolver.caltech.edu/CaltechAUTHORS:20150109-113726556Scaling of MOS Technology to Submicrometer Feature Sizes
https://resolver.caltech.edu/CaltechAUTHORS:20150109-120856432
Year: 1999
Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion
of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other
technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology
is reduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at the
system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude
with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.https://resolver.caltech.edu/CaltechAUTHORS:20150109-120856432Life Without Bits
https://resolver.caltech.edu/CaltechAUTHORS:20150112-152455731
Year: 1999
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150112-152455731A Bidirectional Analog VLSI Cochlear Model
https://resolver.caltech.edu/CaltechAUTHORS:20150112-115633935
Year: 1999
A novel circuit is presented for implementing a bidirectional passive cochlear
model in analog VLSI. The circuit includes a subcircuit for modelling the
fluid in the cochlear duct, and a subcircuit for modelling the passive basilar
membrane. The circuit is compared to the classical 1-D transmission
line cochlear model and found to be equivalent. The approach leads to
an unexpected fa.ult tolerance in the form of insensitivity to transconductance
amplifier offset voltages. A 545-stage cochlea has been fabricated and
demonstrates the expected wave propagation behaviour.https://resolver.caltech.edu/CaltechAUTHORS:20150112-115633935Collective electrodynamics : quantum foundations of electromagnetism
https://resolver.caltech.edu/CaltechAUTHORS:20150203-162438256
Year: 2000
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150203-162438256The Evolution of Electronic Photography
https://resolver.caltech.edu/CaltechAUTHORS:20150112-110810021
Year: 2001
Silver-based photography was invented in the mid-1800s,
and has existed in its modem form for over 100 years.
More than 60 million film cameras will be sold this year, a
larger number than for any previous year. In spite of the
explosion in digital technology for other applications,
digital camera technology still produces images that arc
vastly inferior to film images. Recent developments in
silicon image sensors have made possible the direct capture
of images that exceed the quality of film images.
Over the next decade, cameras based on these
principles will supplant film cameras in nearly all
applications. In many ways, electronic photography has
gone through evolutionary steps closely paralleling those
experienced in the early days of film photography. The
current leading-edge technology will be discussed, with
referenced to its place in the evolutionary sequence.https://resolver.caltech.edu/CaltechAUTHORS:20150112-110810021Cost and Performance of VLSI Computing Structures
https://resolver.caltech.edu/CaltechCSTR:1978.1584-tr-78
Year: 2002
DOI: 10.7907/fm4yx-3bq89
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic Silicon chip. What will the nature of such systems be? How will they be designed? What will be their cost and performance? Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths places a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. Two illustrative systems are analyzed in detail: a RAM based system and an associative system. It is shown that in each case an optimum design is possible, using the area – time product as a cost function.https://resolver.caltech.edu/CaltechCSTR:1978.1584-tr-78Neuromorphic Engineering: Overview and Potential
https://resolver.caltech.edu/CaltechAUTHORS:20150126-165023417
Year: 2005
DOI: 10.1109/IJCNN.2005.1556463
It is evident to even the most casual observer that the
nervous systems of animals are able to accomplish feats
that cannot be approached by our most powerful
computing systems. Given the exponential increase in
computing power over the last 45 years, our inability to
rival the common housefly has become downright
embarrassing. What is going on?https://resolver.caltech.edu/CaltechAUTHORS:20150126-165023417A notation for designing restoring logic circuitry in CMOS
https://resolver.caltech.edu/CaltechCSTR:1981.4600-tr-81
Year: 2008
We introduce a programming notation in which every syntactically correct program specifies a restoring logic component, i.e., a component whose outputs are permanently connected, via "not too many" transistors, to the power supply. It is shown how the specified components can be translated into transistor diagrams for CMOS integrated circuits. As these components are designed as strict hierarchies, it is hoped that the translation of the transistor diagrams into layouts for integrated circuits can be accomplished mechanically.https://resolver.caltech.edu/CaltechCSTR:1981.4600-tr-81Optimum Noise Performance of Transistor Input Circuits / Transistor AC and DC Amplifiers with High Input Impedance
https://resolver.caltech.edu/CaltechAUTHORS:20121108-143232418
Year: 2012
Some results are presented for optimum noise performance of transistor input stages when fed from resistive or reactive sources. Standard theory has shown that a common-emitter transistor fed from a resistive source presents a minimum noise figure F_m when the source resistance has a certain value R_gm in the order of lkΩ. In this
paper, expressions are developed for minimum noise figure and optimum
source resistance in the presence of base bias resistors, emitter degeneration
resistance, and various kinds of feedback. Results are in
terms of F_m and R_gm only, and do not contain other functions of the
transistor internal noise sources. It is shown that the minimum noise
figure is never less than F_m, but the optimum source resistance can be
either greater or less than R_gm.
In the case of reactive sources, noise figure is meaningless and
the quantity of interest is signal-to-noise ratio over the passband.
It is shown that for an inductive source, such as a magnetic tape head,
there is a maximum signal-to-noise ratio obtainable with an optimum
source inductance, and that a Figure of Merit can be assigned to the
source which is independent of its inductance.
Experimental results presented for both resistive and inductive
sources show good agreement with the theoretical predictions.https://resolver.caltech.edu/CaltechAUTHORS:20121108-143232418The evolution of technology
https://resolver.caltech.edu/CaltechAUTHORS:20150127-163653667
Year: 2013
DOI: 10.1109/ISSCC.2013.6487621
Faraday's Law of induction gave us generators, motors, telegraph, telephone, etc. The vacuum tube gave us long-distance telephone, radio, hi-fi audio, television, and early computers. Microcircuits have given us personal computers, cell phones, the Internet, and GPS positioning.
Now, What?https://resolver.caltech.edu/CaltechAUTHORS:20150127-163653667The Nature of Light: What are "Photons"?
https://resolver.caltech.edu/CaltechAUTHORS:20131209-074730086
Year: 2013
DOI: 10.1117/12.2046381
We are told that our present understanding of physical law was ushered in by the Quantum Revolution, which began around 1900 and was brought to fruition around 1930 with the formulation of modern Quantum Mechanics. The "photon" was supposed to be the centerpiece of this revolution, conveying much of its conceptual flavor. What happened during that period was a rather violent redirection of the prevailing world view in and around physics - a process that has still not settled. In this paper I critically review the evolution of the concepts involved, from the time of Maxwell up to the present day. At any given time, discussions in and around any given topic take place using a language that presupposes a world view or zeitgeist. The world view itself limits what ideas are expressible. We are all prisoners of the language we have created to develop our understanding to its present state. Thus the very concepts and ways of thinking that have led to progress in the past are often the source of blind spots that prevent progress into the future. The most insidious property of the world view at any point in time is that it involves assumptions that are not stated. In what follows we will have a number of occasions to point out the assumptions in the current world view, and to develop a new world view based on a quite different set of assumptions.https://resolver.caltech.edu/CaltechAUTHORS:20131209-074730086Detecting beyond-Einstein polarizations of continuous gravitational waves
https://resolver.caltech.edu/CaltechAUTHORS:20150519-072427452
Year: 2015
DOI: 10.1103/PhysRevD.91.082002
The direct detection of gravitational waves with the next-generation detectors, like Advanced LIGO, provides the opportunity to measure deviations from the predictions of general relativity. One such departure would be the existence of alternative polarizations. To measure these, we study a single detector measurement of a continuous gravitational wave from a triaxial pulsar source. We develop methods to detect signals of any polarization content and distinguish between them in a model-independent way. We present LIGO Science Run 5 sensitivity estimates for 115 pulsars.https://resolver.caltech.edu/CaltechAUTHORS:20150519-072427452Gravitational Waves in G4v
https://resolver.caltech.edu/CaltechAUTHORS:20150819-134952067
Year: 2015
DOI: 10.48550/arXiv.1503.04866
Gravitational coupling of the propagation four-vectors of matter wave functions is formulated in at space-time. Coupling at the momentum level rather than at the "force-law" level greatly simplifies many calculations. This locally Lorentz-invariant approach (G4v) treats electromagnetic and gravitational coupling on an equal footing. Classical mechanics emerges from the incoherent aggregation of matter wave functions. The theory reproduces, to first order beyond Newton, the
standard GR results for Gravity-Probe B, deflection of light by massive bodies, precession of orbits, gravitational red shift, and total gravitational-wave energy radiated by a circular binary system. Its predictions differ markedly from GR for the gravitational-wave radiation patterns from rotating massive systems, and for the LIGO antenna pattern. G4v predictions of total radiated energy from highly eccentric Kepler systems are slightly larger than those of similar GR treatments. A detailed treatment of the theory is in preparation. However the generation and detection of gravitational waves is exactly the same as the corresponding treatment for electromagnetic waves given in
Collective Electrodynamics, (hereinafter referred to simply as CE) and therefore separable from the material in preparation. It therefore seems advisable to make the gravitational-wave material available, since
its predictions should be testable as data from Advanced LIGO becomes available over the next few years. The presentation is somewhat more detailed than would be "normal," simply to make the approach clear and accessible to non-specialists.https://resolver.caltech.edu/CaltechAUTHORS:20150819-134952067Analog VLSI Phototransduction by continuous-time, adaptive, logarithmic photoreceptor circuits
https://resolver.caltech.edu/CaltechAUTHORS:20150908-164952926
Year: 2015
Over the last few years, we and others have built a number of interesting neuromorphic analog vision chips that do focal-plane time-domain computation. These chips do local, continuous-time, spatiotemporal processing that takes place before any sampling or long-range communication, for example, motion processing, change detection, neuromorphic retinal preprocessing, stereo image matching, and synthesis of auditory images from visual scenes.
This processing requires photoreceptor
circuits that transduce from light falling on
the chip to an electrical signal. If we want
to build analog vision chips that do high-quality
focal plane processing, then we
need good photoreceptors. It's not enough
to just demonstrate a concept; ultimate usefulness
will be determined by market forces,
which, among other factors, depend a
lot on raw performance. The receptor circuits
we discuss here have not been used in
any commercial product, so they have not
yet passed that most crucial test, but by every
performance metric we can come up
with, including successful fabrication and
test of demonstration systems, they match
performance criteria met by other phototransduction
techniques that are used in
end-product consumer electronic devices.
We hope that this article will serve several
purposes: We want people to have a reference
where they can look to see the
functioning and practical problems of phototransducers
built in a typical CMOS or
BiCMOS process. We want to inspire people
to build low-power, integrated commercial
vision devices for practical
purposes. We want to provide a photoreceptor
that can be used as a front end transducer
in more advanced research on
neuromorphic systems.
The transduction process seems mundane,
but it is important --GIGO comes to
mind. Subsequent computation relies on the
information. We don't know of any contemporary
(VLSI-era) literature that comprehensively
explore the subject. Previous
results are lacking in some aspect, either in
the circuit itself, or in the understanding of
the physics, or in the realistic measurement
of limitations on behavior.
We'll focus on one highly-evolved adaptive
receptor circuit to understand how it
operates, what are the limitations on its dynamic
range, and what is the physics of the
noise behavior. The receptor has new and
previously unpublished technical improvements,
and we understand the noise properties
and illumination limits much better
than we did before. We'll also discuss the
practical aspects of the interaction of light
with silicon: What are the spectral responses
of various devices? How far do light-generated
minority carriers diffuse and how
do they affect circuit operation? How effective
are guard bars to protect against them?
Finally, we'll talk about biological receptors:
How do their functional characteristics
inspire the electronic model? How are the
mechanisms of gain and adaptation related?https://resolver.caltech.edu/CaltechAUTHORS:20150908-164952926Refractory Neuron Circuits
https://resolver.caltech.edu/CaltechAUTHORS:20150908-164345500
Year: 2015
Neural networks typically use an abstraction of the behaviour of a biological neuron, in which
the continuously varying mean firing rate of the neuron is presumed to carry information about
the neuron's time-varying state of excitation. However, the detailed timing of action potentials is
known to be important in many biological systems. To build electronic models of such systems,
one must have well-characterized neuron circuits that capture the essential behaviour of real
neurons in biological systems. In this paper, we describe two simple and compact circuits that
fire narrow action potentials with controllable thresholds, pulse widths, and refractory periods.
Both circuits are well suited as high-level abstractions of spiking neurons. We have used the first
circuit to generate action potentials from a current input, and have used the second circuit to
delay and propagate action potentials in an axon delay line. The circuit mechanisms are derived
from the behaviour of sodium and potassium conductances in nerve membranes of biological
neurons. The first circuit models behaviours at the axon hillock; the second circuit models
behaviour at the node of Ranvier in biological neurons. The circuits have been implemented in
a 2-micron double-poly CMOS process. Results are presented from working chips.https://resolver.caltech.edu/CaltechAUTHORS:20150908-164345500Optical Flow and Surface Interpolation in Resistive Networks: Algorithms and Analog VLSI Chips
https://resolver.caltech.edu/CaltechAUTHORS:20151029-101037556
Year: 2015
To us, and to other biological organisms, vision seems effortless. We open our eyes and we "see" the world in all its color, brightness, and movement. Flies, frogs, cats, and humans can all equally well perceive a rapidly changing environment and act on it. Yet, we have great difficulties when trying to endow our machines with similar abilities. In this article, we describe
recent developments in the theory of early vision that led from the formulation of the motion problem as an ill-posed one to its solution by minimizing certain "cost" functions. These cost or energy functions can be mapped onto simple analog and digital resistive networks. For instance, as
detailed in this chapter, we can compute the optical flow by injecting currents into resistive networks and recording the resulting stationary voltage distribution at each node. These networks, which are implemented in subthreshold, analog, complementary metal oxide semiconductor (CMOS) very
large scale integrated (VLSI) circuits, are very attractive for their technological potential.https://resolver.caltech.edu/CaltechAUTHORS:20151029-101037556How we created neuromorphic engineering
https://resolver.caltech.edu/CaltechAUTHORS:20200625-085609229
Year: 2020
DOI: 10.1038/s41928-020-0448-2
Neuromorphic engineering aims to create computing hardware that mimics biological nervous systems, and it is expected to play a key role in the next era of hardware development. Carver Mead recounts how it all began.https://resolver.caltech.edu/CaltechAUTHORS:20200625-085609229Symmetry, Transactions, and the Mechanism of Wave Function Collapse
https://resolver.caltech.edu/CaltechAUTHORS:20200625-075535642
Year: 2020
DOI: 10.3390/sym12081373
The Transactional Interpretation of quantum mechanics exploits the intrinsic time-symmetry of wave mechanics to interpret the ψ and ψ* wave functions present in all wave mechanics calculations as representing retarded and advanced waves moving in opposite time directions that form a quantum "handshake" or transaction. This handshake is a 4D standing-wave that builds up across space-time to transfer the conserved quantities of energy, momentum, and angular momentum in an interaction. Here, we derive a two-atom quantum formalism describing a transaction. We show that the bi-directional electromagnetic coupling between atoms can be factored into a matched pair of vector potential Green's functions: one retarded and one advanced, and that this combination uniquely enforces the conservation of energy in a transaction. Thus factored, the single-electron wave functions of electromagnetically-coupled atoms can be analyzed using Schrödinger's original wave mechanics. The technique generalizes to any number of electromagnetically coupled single-electron states—no higher-dimensional space is needed. Using this technique, we show a worked example of the transfer of energy from a hydrogen atom in an excited state to a nearby hydrogen atom in its ground state. It is seen that the initial exchange creates a dynamically unstable situation that avalanches to the completed transaction, demonstrating that wave function collapse, considered mysterious in the literature, can be implemented with solutions of Schrödinger's original wave mechanics, coupled by this unique combination of retarded/advanced vector potentials, without the introduction of any additional mechanism or formalism. We also analyze a simplified version of the photon-splitting and Freedman–Clauser three-electron experiments and show that their results can be predicted by this formalism.https://resolver.caltech.edu/CaltechAUTHORS:20200625-075535642Carver Mead: "It's All About Thinking," A Personal Account Leading up to the First Microwave Transistor
https://resolver.caltech.edu/CaltechAUTHORS:20210208-144010883
Year: 2021
DOI: 10.1109/jmw.2020.3028277
This article is the second in a continuing series of biographical pieces on individuals who have made significant contributions to microwave science, technology and applications over the course of their careers. It is intended to bring to the reader, especially those new to the field, a portrait of an individual who serves as a role model for the community and a detailed description of their accomplishments. At the same time, it tries to bridge with commonality, the experiences of the subject with those of the scientists, engineers and technologists who are following in their footsteps or hope to establish a similar record of success. The articles are composed only after an extensive face-to-face interview with the subject and are helped immensely by additional input and editing by the subjects themselves. The focus of this article is Caltech Professor Carver A. Mead, perhaps best known for his ground breaking work on VLSI design techniques, but also for the first demonstration of the GaAs MESFET and the originator of Moore's Law. However, Professor Mead has contributed so much more, and to so many disciplines other than electrical engineering. From his own description of his interests and focus, he is a chameleon of knowledge, scrambling into, blending with, and then distinguishing himself in a new field every thirteen years or so, over a career spanning seven decades and still going. At age 86, his latest paper, on an intuitive approach to electromagnetically coupled single-electron quantum systems, was just published this summer. Although we cannot do justice to all his contributions, we hope the reader will see something of the polymath in Professor Mead as we focus just on his earliest work, where he single handedly conceived, constructed, and tested the world's first Schottky barrier gate transistor in his modest laboratory at Caltech.https://resolver.caltech.edu/CaltechAUTHORS:20210208-144010883My Early Collaboration with Bill Goddard
https://resolver.caltech.edu/CaltechAUTHORS:20210127-082657092
Year: 2021
DOI: 10.1007/978-3-030-18778-1_3
In 1962, I struck up a collaboration with Bill Goddard and several solid-state physics labs to do a systematic study of the properties of metal-semiconductor junctions. These structures are ubiquitous in semiconductor devices and are central to their operation. Understanding them is at the boundary of Physics and Chemistry.https://resolver.caltech.edu/CaltechAUTHORS:20210127-082657092Symmetry, Transactions, and the Mechanism of Wave Function Collapse
https://resolver.caltech.edu/CaltechAUTHORS:20220114-163105179
Year: 2022
DOI: 10.3390/books978-3-0365-2695-9
The Transactional Interpretation of quantum mechanics exploits the intrinsic time-symmetry of wave mechanics to interpret the ψ and ψ* wave functions present in all wave mechanics calculations as representing retarded and advanced waves moving in opposite time directions that form a quantum "handshake" or transaction. This handshake is a 4D standing-wave that builds up across space-time to transfer the conserved quantities of energy, momentum, and angular momentum in an interaction. Here, we derive a two-atom quantum formalism describing a transaction. We show that the bi-directional electromagnetic coupling between atoms can be factored into a matched pair of vector potential Green's functions: one retarded and one advanced, and that this combination uniquely enforces the conservation of energy in a transaction. Thus factored, the single-electron wave functions of electromagnetically-coupled atoms can be analyzed using Schrödinger's original wave mechanics. The technique generalizes to any number of electromagnetically coupled single-electron states—no higher-dimensional space is needed. Using this technique, we show a worked example of the transfer of energy from a hydrogen atom in an excited state to a nearby hydrogen atom in its ground state. It is seen that the initial exchange creates a dynamically unstable situation that avalanches to the completed transaction, demonstrating that wave function collapse, considered mysterious in the literature, can be implemented with solutions of Schrödinger's original wave mechanics, coupled by this unique combination of retarded/advanced vector potentials, without the introduction of any additional mechanism or formalism. We also analyze a simplified version of the photon-splitting and Freedman–Clauser three-electron experiments and show that their results can be predicted by this formalism.https://resolver.caltech.edu/CaltechAUTHORS:20220114-163105179Neuromorphic Engineering: In Memory of Misha Mahowald
https://resolver.caltech.edu/CaltechAUTHORS:20221128-1670000.2
Year: 2022
DOI: 10.1162/neco_a_01553
We review the coevolution of hardware and software dedicated to neuromorphic systems. From modest beginnings, these disciplines have become central to the larger field of computation. In the process, their biological foundations become more relevant, and their realizations increasingly overlap. We identify opportunities for significant steps forward in both the near and more distant future.https://resolver.caltech.edu/CaltechAUTHORS:20221128-1670000.2Neuromorphic Engineering: In Memory of Misha Mahowald
https://resolver.caltech.edu/CaltechAUTHORS:20230303-961872000.2
Year: 2023
DOI: 10.1162/neco_a_01553
Abstract
We review the coevolution of hardware and software dedicated to neuromorphic systems. From modest beginnings, these disciplines have become central to the larger field of computation. In the process, their biological foundations become more relevant, and their realizations increasingly overlap. We identify opportunities for significant steps forward in both the near and more distant future.https://resolver.caltech.edu/CaltechAUTHORS:20230303-961872000.2Engineering View of Gravitation
https://resolver.caltech.edu/CaltechAUTHORS:20230321-161151363
Year: 2023
DOI: 10.7907/me3d-6f20
We describe here an internally-consistent, Quantum coupled treatment of gravitation and electromagnetism. The electromagnetic part is put forth in Collective Electrodynamics—Quantum Foundations of Electromagnetism [44], hereinafter referred to as CE, and described briefly in Section 1.3.1. The Gravitational theory described in this document, which we call G4v, is a direct extension of Einstein's 1911/12 approach. It differs from previous attempts in a number of important ways:
• Neither the electromagnetic nor gravitational fields are quantized.
The wave functions and four-potentials are continuous functions of space and time.
Quantization results from the interaction of matter and field wave functions.
• The theory is based on Mach's Principle and provides a conceptual base for the Equivalence Principle.
• It is not a metric theory; it is formulated in flat space-time.
Lengths are constant and do not vary with gravitation potential
• The speed of light c is equal to the gravitational scalar potential.
It is not constant, but varies with position and time.
• The quantity of matter coupled gravitationally is not the mass m.
It is the Compton wave number k0 = mc/~.
• The theory is based on four-vector coupling.
It is thus locally Lorentz-invariant in regions where the speed of light can be considered constant.
• The source of the electrical four-potential is the charge–current density four-vector, and that for the
gravitational four potential is the energy-momentum four-vector. Both quantities are defined for the wave
function of the source matter, and appear as terms in the affected matter wave function.
The concept of force is not necessary, but can be computed if desired.https://resolver.caltech.edu/CaltechAUTHORS:20230321-161151363Potential Major Improvement in Superconductors for High-Field Magnets
https://resolver.caltech.edu/CaltechAUTHORS:20230414-212445417
Year: 2023
DOI: 10.48550/arXiv.2304.06171
Fusion reactors are limited by the magnetic field available to confine their plasma. The commercial fusion industry uses the larger magnetic field and higher operating temperature of the cuprate superconductor YBa₂Cu₃O_(7−δ) (YBCO) in order to confine their plasma into a dense volume. A superconductor is a macroscopic quantum state that is protected from the metallic (resistive) state by an energy gap. Unfortunately, YBCO has an anisotropic gap, known as D-wave because it has the shape of a d_(x²−y²) chemical orbital. This D-wave gap means that poly-crystalline wire cannot be made because a few degree misalignment between grains in the wire leads to a drastic loss in its supercurrent carrying ability, and thereby its magnetic field limit. The superconductor industry has responded by growing nearly-single-crystal superconducting YBCO films on carefully prepared substrate tapes kilometers in length. Heroic development programs have made such tapes commercially available, but they are very expensive and delicate. MRI magnet superconductors, such as NbTi and Nb3Sn, are formed into poly-crystalline wires because they have an isotropic gap in the shape of an s chemical orbital (called S-wave) that makes them insensitive to grain misalignment. However, these materials are limited to lower magnetic fields and liquid-He temperatures. Here, we modified YBCO by doping the Y site with Ca and Ce atoms to form (Y₁₋ₓ₋ᵧCaₓCeᵧ)Ba₂Cu₃O_(7−δ), and show evidence that it changes to an S-wave gap. Its superconducting transition temperature, T꜀, of ∼70K, while lower than that of D-wave YBCO at ∼90K, is easily maintained using common, economic cryogenic equipment.https://resolver.caltech.edu/CaltechAUTHORS:20230414-212445417A Simple Cosmology in G4v
https://resolver.caltech.edu/CaltechAUTHORS:20230627-482016000.2
Year: 2023
DOI: 10.3390/sym15071309
There has been a great deal of debate as to the role, if any, of Mach's Principle in cosmology. We propose that these questions have meaning only in the context of a cosmic gravitational potential. G4v operates with such a four-potential, which imposes a different symmetry on its treatment of light propagation than that employed by GR. That combination enables a simple cosmic solution that is Lorentz-invariant in free-fall frames of reference. The solution is compared with supernovae data, which, together with an internal self-consistency condition, fixes the parameters of the solution. The resulting Hubble trajectory is, in broad brush, consistent with many cosmic observations.https://resolver.caltech.edu/CaltechAUTHORS:20230627-482016000.2Propagation of pulsed light in an optical cavity in a gravitational field
https://authors.library.caltech.edu/records/rtkg1-zce31
Year: 2024
DOI: 10.48550/arXiv.2408.03384
<p>All modern theories of gravitation, starting with Newton's, predict that gravity will affect the speed of light propagation. Einstein's theory of General Relativity famously predicted that the effect is twice the Newtonian value, a prediction that was verified during the 1919 solar eclipse. Recent theories of vector gravity can be interpreted to imply that gravity will have a different effect on pulsed light versus continuous-wave (CW) light propagating between the two mirrors of an optical cavity. Interestingly, we are not aware of any previous experiments to determine the relative effect of gravity on the propagation of pulsed versus CW light. In order to observe if there are small differences, we use a 6 GHz electro-optic frequency comb and low-noise CW laser to make careful measurements of the resonance frequencies of a high-finesse optical cavity. Once correcting for the effects of mirror dispersion, we determine that the cavity resonance frequencies for pulsed and CW light are the same to within our experimental error, which is on the order of 10⁻<span class="legacy-color-text-default">¹</span><span class="legacy-color-text-default">² </span><span class="MathJax"><span class="math"><span class="mrow"><span class="msubsup"><span class="texatom"><span class="mrow"><span class="mn">of the optical frequency, and one part in 700 of the expected gravitational shift.</span></span></span></span></span></span></span></p>https://authors.library.caltech.edu/records/rtkg1-zce31