CaltechAUTHORS: Book Chapter
https://feeds.library.caltech.edu/people/Mead-C-A/book_section.rss
A Caltech Library Repository Feedhttp://www.rssboard.org/rss-specificationpython-feedgenenMon, 14 Oct 2024 07:28:59 -0700Electron Transport in Thin Insulating Films
https://resolver.caltech.edu/CaltechAUTHORS:20150902-160503489
Year: 1966
Experiments on the electron transport through thin insulating barriers have been performed with
diodes of Ta-Ta_2O_5-Au, Ta-Ta_2O_5-Al, Ta-Ta_2O_5-Bi, Zn-ZnO-Au, Al-Al_2O_3-Al and Al-Al_2O_3-Au.
The analysis of the dependence of current on temperature and film thickness allows a distinction
of two cases: imperfect and perfect dielectrics. In the former case the mechanism for electron
transport is field ionisation of trap-type states at low temperatures and thermal ionisation of this
states at higher temperatures. In the latter case Schottky-Emission and field emission have been
observed.https://resolver.caltech.edu/CaltechAUTHORS:20150902-160503489Some Properties of Exponentially Damped Wave Functions
https://resolver.caltech.edu/CaltechAUTHORS:20150223-145247878
Year: 1969
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150223-145247878Physics of Interfaces
https://resolver.caltech.edu/CaltechAUTHORS:20150223-144739659
Year: 1969
It has long been known that when a metal is placed in contact with a semiconductor a rectifying contact often results. This rectification is a result
of an energy barrier between the metal and the semiconductor. In order to form a nonrectifying or ohmic contact, two general approaches can be applied: either (1) the barrier energy can be reduced to a low
enough value that the thermally excited current over the barrier is large enough for the application involved or (2) the semiconductor can be doped to a high carrier density to allow quantum mechanical tunneling to take
place. The physical principles of these processes are discussed in this article.https://resolver.caltech.edu/CaltechAUTHORS:20150223-144739659Electronic Current Flow Through Ideal Dielectric Films
https://resolver.caltech.edu/CaltechAUTHORS:20151007-110001781
Year: 1972
During the past few decades a large literature has accumulated on the subject of current flow through dielectric films. Much of this material contains detailed analyses of many physical effects and a
great deal of multiparameter curve fitting. Until recently all this activity had given the field a rather bad name, since it appeared that all effects were very complicated and nothing could be understood in a first-principles way. It is true, in fact, that in many thin-film
systems the current flow is dominated by impurities, trapping processes, and so on, so that no simple, clear picture emerges for the mechanism of current flow. However, in the past few years it has become clear that certain insulating materials behave in a nearly ideal
fashion and can be understood in a very simple and fundamental way.
In this chapter I shall not attempt to discuss the mass of literature dealing with data on dielectrics that were not well characterized and well understood. Instead, I shall concentrate on examples in which nearly ideal behavior was observed and in which the simple physics of the current-flow processes is clear. In retrospect it seems
obvious that much of the previous data is also understandable on rather simple grounds and that there were a number of conceptual errors that led to the belief that vastly complicated processes were involved. This is by no means true for all the data in the literature,
but certainly with good hindsight resulting from a clear understanding of ideal materials, a much better understanding of the nonideal cases
is also possible. Since the details of all the results I shall cite are available in the published literature, I shall discuss only the ideas and basic principles involved and give references where a more complete
discussion may be found.https://resolver.caltech.edu/CaltechAUTHORS:20151007-110001781Charge transfer in charge-coupled devices
https://resolver.caltech.edu/CaltechAUTHORS:20150114-110748689
Year: 1972
DOI: 10.1109/ISSCC.1972.1155057
Previous theoretical work on the operation of charge-coupled devices has been rather qualitative. These studies emphasize one of a number of factors which can influence the charge-transfer process, for example, nonlinear diffusion and fringing fields. However, none of these studies take account of all the factors in a realistic way.https://resolver.caltech.edu/CaltechAUTHORS:20150114-110748689ESP, A Distributed Architecture LSI Machine
https://resolver.caltech.edu/CaltechAUTHORS:20151008-160932933
Year: 1974
The Externally Sequenced Processor
(ESP) is a system which embodies a complete
separation of the control and data processing
functions of the machine. The ESP is
organized so that additional functional capabilities
as well as peripherals can be added.
The interfacing requirements are particularly
straightforward.https://resolver.caltech.edu/CaltechAUTHORS:20151008-160932933Single-Chip Cursive Character Generator
https://resolver.caltech.edu/CaltechAUTHORS:20150927-233249188
Year: 1975
DOI: 10.1109/ISSCC.1975.1155385
A unique circuit design using conventional MOS technology
has been found to yield a sequential read-only analog
memory which can generate the x- and y-axis deflection
voltages for the stroke-by-stroke synthesis of
alphanumeric characters.https://resolver.caltech.edu/CaltechAUTHORS:20150927-233249188A critical look at microprocessor architecture
https://resolver.caltech.edu/CaltechAUTHORS:20170808-170646928
Year: 1975
DOI: 10.1109/ISSCC.1975.1155410
LSI has provided machine designers a medium of unprecedented power and versatility. The potential of this technology has been doubling every year and promises to continue for another factor of 1000. It is inevitable that such potential will be used to achieve ever more powerful machine organizations and will, in the long run, totally change our basic concepts of machine structure and function. To date, however, the microprocessors which have been implemented are of a very conventional type. This trend poses several fundamental questions.https://resolver.caltech.edu/CaltechAUTHORS:20170808-170646928ESP, A Distributed Architecture LSI Machine
https://resolver.caltech.edu/CaltechAUTHORS:20151008-160109295
Year: 1976
The Externally Sequenced Processor (ESP) is a system that embodies a complete separation
of the control and data processing functions of the machine. The ESP is organized
so that additional functional capabilities as well as peripherals can be added. The
interfacing requirements are particularly straightforward.https://resolver.caltech.edu/CaltechAUTHORS:20151008-160109295A two's complement pipeline multiplier
https://resolver.caltech.edu/CaltechAUTHORS:20150120-163927542
Year: 1976
DOI: 10.1109/ICASSP.1976.1169990
A serial-data pipeline multiplier was designed and implemented in p-channel silicon-gate MOS. It uses a radix-4 Booth algorithm for two's complement compatibility. The circuit is modular, and is configured to multiply one data word by two coefficient words simultaneously.https://resolver.caltech.edu/CaltechAUTHORS:20150120-163927542Cost and Performance of VLSI Computing Structures
https://resolver.caltech.edu/CaltechAUTHORS:20150927-230413213
Year: 1978
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic
silicon chip. What will the nature of such systems be? How will they be designed? What will be their
cost and performance?
Conducting paths are required for communicating information throughout any integrated system. The
length and organization of these communication paths places a lower bound on the area and time required
for system operations. Optimal designs can be achieved in only a few of the many alternative structures.
A random access memory is analyzed in detail as an example. It is shown that in each case an optimum
design is possible, using the area - time product as a cost function.https://resolver.caltech.edu/CaltechAUTHORS:20150927-230413213VLSI and Technological Innovation
https://resolver.caltech.edu/CaltechAUTHORS:20150213-105251082
Year: 1979
VLSI relies on a range of disciplines for its successful implementation. Two of the most important of these are still in their infant stages. A. Design methodologies to manage complexity. B. Architecture of ultra concurrent machines. Innovation in infant disciplines occurs most rapidly and successfully when a large number of small groups proceed independently under the motivation of market opportunity. In a few years, a substantial fraction of the engineering work force will have a working knowledge of LSI design. At the same time, fabrication areas are becoming more and more capital intensive. What is needed is a clean, standard interface between a multitude of small diverse VLSI design groups and a few state-of-the-art fabrication suppliers. A proposal for such an interface is presented in this article.https://resolver.caltech.edu/CaltechAUTHORS:20150213-105251082Cost and Performance of VLSI Computing Structures
https://resolver.caltech.edu/CaltechAUTHORS:20150223-143648166
Year: 1981
Using VLSI technology, it will soon be possible to implement
entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of
the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time
product as a cost function.https://resolver.caltech.edu/CaltechAUTHORS:20150223-143648166VLSI and Technological Innovations
https://resolver.caltech.edu/CaltechAUTHORS:20150927-230856422
Year: 1981
Rather than innovation in general, I will discuss what I believe
to be the most important opportunity since the industrial
revolution, rivalling it in significance. This unique circumstance
is created by the emerging Very Large Scale Integrated
(VLSI) technology, with which enormously complex digital
electronic systems can be fabricated on a single chip of
Silicon one-tenth the size of a postage stamp. Out of it
systems will be created which radically change our modes of
communication, commerce, education, entertainment, science and
the underlying rate of cultural evolution. The quality of
human life can be improved in remarkable ways by these changes.
Electronics creates no noxious by-products and uses only miniscule
amounts of energy. It can accomplish tasks which were
previously energy intensive, and dangerous or degrading to
human workers. There is no doubt that this electronic revolution
will take place.https://resolver.caltech.edu/CaltechAUTHORS:20150927-230856422Minimum Propagation Delays in VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150213-103145341
Year: 1981
With feature sizes decreasing and chip area increasing it becomes more and more time consuming to transport signals over long distances across the chip [5]. Designers are already introducing more levels of metal connections, using wider and thicker paths for longer distances. Another recent development is the introduction of an additional level of connections between the chip and the pc-board, multilayer ceramic chip carriers. The trend is undoubtedly towards even more connecting levels. In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light.https://resolver.caltech.edu/CaltechAUTHORS:20150213-103145341Bit-Serial Inner Product Processors in VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150212-162610645
Year: 1981
In this paper we describe a bit-serial pipelined implementation of an inner product processor, and related interconnections of a number of such processors on a single chip. We argue that bit-serial computational models are particularly suited for VLSI, because of relatively inexpensive communication links and arithmetic processing elements, in terms of the area occupied on silicon. Sixteen inner product processors, described here, may be easily placed on a single 40-pin chip in today's NMOS technology with a 2 micron lambda. Similar arguments for bitserial arithmetic were used in [3]. in a description of a design of a general purpose massively parallel processor.https://resolver.caltech.edu/CaltechAUTHORS:20150212-162610645A Notation for Designing Restoring Logic Circuitry in CMOS
https://resolver.caltech.edu/CaltechAUTHORS:20150213-104643106
Year: 1981
We introduce a programming notation in which every syntactically correct program specifies a restoring logic component, i.e., a component whose outputs are permanently connected, via "not too many" transistors, to the power supply. It is shown how the specified components can be translated into transistor diagrams for CMOS integrated circuits . As these components are designed as strict hierarchies, it is hoped that the translation of the transistor diagrams into layouts for integrated circuits can be accomplished mechanically.https://resolver.caltech.edu/CaltechAUTHORS:20150213-104643106Structural and Behavioral Composition of VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150310-154750071
Year: 1983
VLSI design requires all of the complexity management discipline associated with complex
software systems, but without the underlying simplicity of a single sequential machine. Not only must we deal with the problems of enormous concurrency, but we
must map the entire design onto a physical medium, with real constraints on space, time,
and energy imposed by the laws of physics.https://resolver.caltech.edu/CaltechAUTHORS:20150310-154750071VLSI Circuit as Communicating Processes: A Universal Simulator
https://resolver.caltech.edu/CaltechAUTHORS:20150223-144315648
Year: 1983
A VLSI system is represented as a hierarchy of
modules. These modules range from analog models
of circuit elements to systems such as systolic arrays
and tree machines. Though these elements are of
drastically different natures, they share the property
of being autonomous processes, each performing a sequence
of events and communicating with one another.
This metaphor has been developed as a formal model
of computation; any computational system can be
described in these terms. We describe a simulator
which is built upon this metaphor. Central to the
simulator is a fixed-point algorithm which finds the
steady state of the system. Since in both theory and
practice it is capable of handling all levels of design,
we call it a universal simulator.https://resolver.caltech.edu/CaltechAUTHORS:20150223-144315648A Hierarchical Simulator Based on Formal Semantics
https://resolver.caltech.edu/CaltechAUTHORS:20150130-160953426
Year: 1983
Simulation consists of exercising the representation of a design on a general purpose computer. It differs from programming only because the ultimate implementation will be in a different medium, say a VLSI chip. In order for simulation to be in any sense effective, the simulated
system must perform the same function as the ultimate implementation. A VLSI chip is a highly concurrent object; the simulation of such a chip amounts to programming a highly concurrent system. It follows that any
demonstrably correct simulation technique will be one of the two types:
(1) The entire design is represented as an implementation with objects which are abstract models of the medium at the bottom level (e.g. transistor model). The simulation operates on a representation which is a direct image of the fully instantiated implementation in the medium.
(2) The design is represented as a hierarchy of implementations. Each level of implementation is constructed of objects which are abstract models of the implementation at the level below it. The
simulation operates on a hierarchical representation where each level is refined by the level below it.https://resolver.caltech.edu/CaltechAUTHORS:20150130-160953426Pooh: A Uniform Representation For Circuit Level Designs
https://resolver.caltech.edu/CaltechAUTHORS:20150310-155318797
Year: 1983
This paper describes a simple but general, technology independent representation for VLSI circuits which maintains connectivity, circuit schematic, and mask geometry
information. A transistor level cell is represented as the interconnection of devices along with their types, sizes and placement, and the cell's typed ports. Connection is represented explicitly by shared connection points. A file of technology dependent information indicates how to implement each transistor type, interconnect type and connection point type, as well as how structure types may
interact.https://resolver.caltech.edu/CaltechAUTHORS:20150310-155318797Concurrent Algorithms as Space-time Recursion Equations
https://resolver.caltech.edu/CaltechAUTHORS:20150318-140330182
Year: 1983
In this paper, we describe a methodology and a single notation for the specification
and verification of synchronous and self-timed concurrent systems ranging from the level
of transistors to communicating processes. The uniform treatment of these systems results
in a powerful abstraction mechanism which allows management of system complexity.https://resolver.caltech.edu/CaltechAUTHORS:20150318-140330182Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits
https://resolver.caltech.edu/CaltechAUTHORS:20150217-161323301
Year: 1984
Modeling digital MOS circuits by RC networks has
become a well accepted practice for estimating delays.
In 1981, Penfield and Rubinstein proposed a method
to bound the waveforms of nodes in an RC tree network.
In this paper, a single value of delay is derived
for any node in a general RC network. The effects of
parallel connections and stored charges are properly
taken into consideration. The algorithms can be
used either as a stand-alone simulator, or as a front
end for producing initial waveforms for waveform-relaxation
based circuit simulators. An experimental
simulator called SDS (Signal Delay Simulator) has
been developed. For all the examples tested so far,
this simulator runs two to three orders of magnitude
faster than SPICE, and detects all transitions and
glitches at approximately the correct time.https://resolver.caltech.edu/CaltechAUTHORS:20150217-161323301A Correlating Optical Motion Detector
https://resolver.caltech.edu/CaltechAUTHORS:20150310-155720165
Year: 1984
Here we describe an optical motion detector that uses
integrated light sensors and analog and digital processing on the same chip. An image of an arbitrary scene or working
surface is sensed by an array of photodiodes, stored, and
correlated with the next image taken on the next cycle.
The position of maximum correlation indicates the relative
motion of the image during the time between samples. This
peak is detected using mutual inhibition and is converted to
digital signals that go off chip to indicate motion. This single
chip motion detector has application in optical mouse
systems. It overcomes certain limitations of present devices
which require a special operating surface. Other potential
uses are in automated vision systems and robotics. This
motion detector could be used, for example, to track parts
moving down an assembly line. We have built a
one-dimensional motion detector and shown it to work in the
laboratory. The design of a two-dimensional version is in
progress.https://resolver.caltech.edu/CaltechAUTHORS:20150310-155720165A Novel Associative Memory Implemented Using Collective Computation
https://resolver.caltech.edu/CaltechAUTHORS:20150310-154028014
Year: 1985
A radically new type of associative memory, the ASSOCMEM, has been implemented in VLSI and tested. Analog circuit techniques are used to construct a network that evolves towards fully restored (digital) fixed-points that are the memories of the system. Association occurs
on the whole source word, each bit of which may assume a continuous analog value. The network does not require the distinction of a search key from a data field in either the source or target words. A key may be dynamically defined by differentially weighting any subset of the source
word. The key need not be exact; the system will evolve to the closest memory. In the case when the key is the whole input word, the system may be thought of as performing error correction.https://resolver.caltech.edu/CaltechAUTHORS:20150310-154028014A New Discipline for CMOS Design: an Architecture for Sound Synthesis
https://resolver.caltech.edu/CaltechAUTHORS:20150223-142831844
Year: 1985
A number of logic forms and clocking schemes for cMOS integrated circuits are in common use. The most common logic form consists of two networks of transistors, the gates of which are connected to the input variables.
An n-channel network defines the boolean condition under which the output is connected to ground (logic zero). A p-channel network defines the complementary condition under which the output is connected to a logical one. Since in many cMOS processes the output of a single
pass transistor cannot be guaranteed to exceed the logic threshold of a typical inverter, pass transistor networks are either forbidden or a complementary transmission gate employing both p and n-channel devices is used.
Clocking schemes for cMOS presently offer tradeoffs over a wide range in the risk vs efficiency space. In one scheme, a single phase clock and its complement are distributed, and used to control either transmission
gates or transistors controlling power to the p and n-channel switching networks. Proper operation in either case requires that the logic delay of the stage exceeds the skew between the two clock lines. In a much safer approach, a two-phase clock is used, both the clock and its complement
being distributed for each phase. In this case risk is eliminated at the expense of doubling the clock wiring. Yet another form is popular in gate-level designs. A single clock is distributed, and locally inverted at masterslave
storage elements. Risk in this case is eliminated at the expense of a minimum storage element employing ten or more transistors.
In this paper we describe a logic form that retains much of the simplicity, elegance, and compactness of the familiar 2-phase nMOS form, with the added advantage of fully static operation. Formal semantics for circuits implemented in this form are easily derived without detailed
circuit or switch-level simulation.https://resolver.caltech.edu/CaltechAUTHORS:20150223-142831844A Methodology for Hierarchical Simulation and Verification of VLSI Systems
https://resolver.caltech.edu/CaltechAUTHORS:20150217-155711452
Year: 1985
We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodology allows (1) a design be decomposed in such a way that more efficient simulation algorithms than
those appeared in most one-level simulators can be employed, (2) abstraction of parts of a design may be
made to reduce the complexity of the entire design. We first give computation models of VLSI designs.
From these models , we derive appropriate algorithms and compare them to illustrate the power of our
methodology. Finally we present the method for ensuring correctness of design at each hierarchical level
and across different levels.https://resolver.caltech.edu/CaltechAUTHORS:20150217-155711452Concurrent Algorithms as Space-Time Recursion Equations
https://resolver.caltech.edu/CaltechAUTHORS:20150302-152631114
Year: 1985
Recent developments in the technology of fabricating large-scale integrated circuits have made it possible to implement computing systems that use many hundred
thousands of transistors to achieve a given task. An interesting design will have high computational complexity rather than merely vast numbers of identical simple components such as memory elements. Such a design can be represented as a fully instantiated implementation of objects of the implementation medium (e.g., transistors
in VLSI technology) or as successive hierarchical levels of implementations where each level is constructed of objects which are abstract models of the implementation
at the level below it. The former allows implementation details at the bottom level to penetrate throughout the whole design. Such representation may be
suited for machine execution but is hard to deal with from the designer's point of view, and verifying both its functionality and physical layout is costly. As the
complexity of the design grows, the limitation of this approach becomes more apparent. The second approach is aimed at managing the complexity of a design.
One breaks the design into successive levels of subsystems until each is of a manageable complexity-the hierarchical design method [11].https://resolver.caltech.edu/CaltechAUTHORS:20150302-152631114A Sensitive Electronic Photoreceptor
https://resolver.caltech.edu/CaltechAUTHORS:20150310-153332443
Year: 1985
The photoreceptors in biological systems give meaningful outputs over about six orders of magnitude of illumination intensity. If we are to build an electronic vision system that is truly useful, it must have a similar dynamic range. The elements of an electronic receptor with many orders of magnitude dynamic range are described below. Experimental
devices were fabricated in p-well cMOS bulk technology through the MOSIS foundry; npn phototransistors with collector connected to substrate are a byproduct of this process. The n-type bulk forms the collector, the p-well is the base, and the n+ diffusion the emitter. In a
typical process, a large transistor of this sort has a current gain β of more than a thousand. Smaller transistors have lower current gains, but are still respectable. The key to very sensitive receptors is to use the current
gain of this very clean bipolar transistor before subjecting the signal to any noise from subsequent amplification stages.https://resolver.caltech.edu/CaltechAUTHORS:20150310-153332443A VLSI Architecture for Sound Synthesis
https://resolver.caltech.edu/CaltechAUTHORS:20150217-164817869
Year: 1985
Sounds that come from physical sources are naturally represented by differential equations in time. Since there is a straightforward correspondence between differential equations in time and finite difference equations, we can
model musical instruments as simultaneous finite difference equations. Musical sounds can be produced by solving the difference equations that model instruments in real time.https://resolver.caltech.edu/CaltechAUTHORS:20150217-164817869A VLSI Approach to Sound Synthesis
https://resolver.caltech.edu/CaltechAUTHORS:20150223-141325251
Year: 1985
We present a VLSI approach to the generation of musical
sounds. This approach allows the generation of very
rich musical sounds using models that are easy to control
and have parameters corresponding to physical attributes
of musical instruments.
Past efforts in musical sound generation have been plagued
with several problems. The computational bandwidth that
is needed to compute musical sounds is enormous, and it is
hopeless to compute sounds in real time on a conventional
general purpose computer. An even larger problem with
previous efforts is the massive bandwidth needed for control
and update of parameters.
Sounds that come from physical sources are naturally represented by differential equations in time. Since there is a straight-forward correspondence between differential equations and finite difference equations, we can model musical instruments as simultaneous finite difference equations. Musical sounds can be produced by solving, in real time, the difference equations that model instruments.
A natural architecture for solving finite difference equations is one with an interconnection matrix between processors that can be reconfigured or "programmed". A realization of a new instrument involves reconfiguring the connection matrix between the processing elements along with configuring connections to the outside world both for control and updates of parameters.
For our basic unit of computation we have chosen a unit we
call a UPE (Universal Processing Element) - it computes
the function:
A + BM + (1 - M)D
We have implemented in nMOS technology a prototype systems
of UPEs and have been successful in implementing
some simple musical instruments on the system of UPEs.https://resolver.caltech.edu/CaltechAUTHORS:20150223-141325251An Integrated Analog Optical Motion Sensor
https://resolver.caltech.edu/CaltechAUTHORS:20150927-224806484
Year: 1986
This paper describes the theory and implementation of an integrated system that
reports the uniform motion of a visual scene. We have built a VLSI circuit that
reports the motion of an image focused directly on it. The chip contains an integrated
photosensor array to sense the image and has closely coupled custom circuits to perform
computation and data extraction.https://resolver.caltech.edu/CaltechAUTHORS:20150927-224806484An Integer Based Hierarchical Representation for VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150112-140550704
Year: 1986
Geometries with 45° line segments are often used in integrated circuit layouts, since they can save considerable area. In the limit, the introduction of 45° lines is only 5% less dense than optimal geometry, i.e. circular geometry, whereas manhattan geometry is 27% less dense [7]. Obviously any actual design cannot
make use of this density factor everywhere - but figure 1 illustrates a simple but common routing problem where the introduction of 45° wires substantially
reduces the area. There has been a trend towards strict manhattan geometries in recent years, however, since it is commonly believed that design rule checking
is complicated by the inclusion of intermediate angles [11, 1, 3, 6]. This paper describes a hierarchical representation that supports a complete circuit description,
but restricts the set of allowable lines to be horizontal, vertical and 45°. Points are constrained to lie on an integer grid. Rather than use arbitrary polygons,
transistors and connection wires are constructed from paths whose sides and ends are created from an octagonal circle approximation. The geometry for contacts is
octagonal and is generated from the same circle approximation. The integer grid and restricted line styles allow the simplification of all the Geometrical Design
Rule (GDR) checking algorithms - for example a square root is not required in the point-point distance calculations, and division is never required. In fact this approach requires less computation than typical manhattan systems. All of the calculations that normally require real number representation are expressed in integers, eliminating any possibility of round-off errors.https://resolver.caltech.edu/CaltechAUTHORS:20150112-140550704VLSI architectures for implementation of neural networks
https://resolver.caltech.edu/CaltechAUTHORS:20141215-164438997
Year: 1986
DOI: 10.1063/1.36247
A large scale collective system implementing a specific model for associative memory was described by Hopfield [1]. A circuit model for this operation is illustrated in Figure 1, and consists of three major components. A collection of active gain elements (called amplifiers or "neurons") with gain function V = g(v) are connected by a passive interconnect matrix which provides unidirectional excitatory or inhibitory connections ("synapses") between the output of one neuron and the input to another. The strength of this interconnection is given by the
conductance G_(ij) = G_0T_(ij). The requirements placed on the gain function g(v) are not very severe [2], and easily met by VLSI-realizable amplifiers. The third circuit element is the capacitances that determine the time evolution of the system, and are modelled as lumped capacitances.
This formulation leads to the equations of motion shown in Figure 2, and to a Liapunov energy function which determines the dynamics of the system, and predicts the location of stable states (memories) in the case of a symmetric matrix T.https://resolver.caltech.edu/CaltechAUTHORS:20141215-164438997SeeHear
https://resolver.caltech.edu/CaltechAUTHORS:20151007-111205800
Year: 1987
The SeeHear is a system designed to help the blind. The heart of the system is a single custom
chip upon which an image is projected by a lens. The function of the system is to map visual
signals from moving objects in the image into auditory signals that can be projected through
earphones to a listener. A sensation is evoked similar to that which the listener would experience
if the moving objects were emitting sound. We hope that the auditory signals provided by the
SeeHear device, in addition to the sound cues already present in the environment, will enable
blind people to create a more detailed internal model of their surroundings than that which can
be extracted from naturally occuring sound cues alone.https://resolver.caltech.edu/CaltechAUTHORS:20151007-111205800Real-Time Visual Computations Using Analog CMOS Processing Arrays
https://resolver.caltech.edu/CaltechAUTHORS:20150203-152114654
Year: 1987
Integration of photosensors and processing elements provides a mechanism to concurrently perform computations previously intractable in real-time. We have used this approach to model biological early vision
processes. A set of VLSI "retina" chips have been fabricated, using large scale analog circuits (over lOOK transistors in total). Analog processing provides sophisticated, compact functional elements,
and avoids some of the aliasing problems encountered in conventional sampled-data artificial vision systems.https://resolver.caltech.edu/CaltechAUTHORS:20150203-152114654A Physical Charge-Controlled Model for MOS Transistors
https://resolver.caltech.edu/CaltechAUTHORS:20150203-154214722
Year: 1987
As MOS devices scale to submicron lengths, short-channel effects become more pronounced, and an improved transistor model becomes a necessary tool for the VLSI designer [10]. We present a simple, physically based charge-controlled model. The current in the MOS transistor is described in terms of the mobile charge in the channel, and incorporates the physical processes of drift and diffusion. The
effect of velocity saturation is included in the drift term. We define a complete set of natural units for velocity, voltage, length, charge, and current. The solution of the dimensionless current-flow equations using
these units is a simple continuous expression, equally applicable in the subthreshold, saturation, and "ohmic" regions of transistor operation, and suitable for computer simulation of integrated circuits. The model is in agreement with measurements on short-channel transistors
down to 0.35μ channel length.https://resolver.caltech.edu/CaltechAUTHORS:20150203-154214722A Two-Dimensional Visual Tracking Array
https://resolver.caltech.edu/CaltechAUTHORS:20150112-121106664
Year: 1988
The density and concurrency available in VLSI make it an excellent technology
for implementing visual image-processing. By incorporating phototransistors
and analog processing elements onto a single die, the large signal
bandwidths required for real-time computations can be achieved. This
paper describes a VLSI chip that computes the "center of intensity" of a
two-dimensional visual field. One application for this network is the localization
of a bright spot of light against a dark background. Theoretical and
experimental results are presented to describe the operation of the system
and its suitability as a input device for tracking servo systems.https://resolver.caltech.edu/CaltechAUTHORS:20150112-121106664Orientation-Selective VLSI Retina
https://resolver.caltech.edu/CaltechAUTHORS:20151012-141538820
Year: 1988
DOI: 10.1117/12.969056
In both biological and artificial pattern-recognition systems, the detection of oriented light-intensity edges is an important preprocessing step. We have constructed a silicon VLSI device containing an array of photoreceptors with additional hardware for computing center-surround (edge-enhanced) response as well as edge orientation at every point in the receptor lattice. Because computing the edge orientations in the array local to each photoreceptor would have made each pixel-computation unit too large (thereby reducing the resolution of the device), we devised a novel technique for computing the orientations outside of the array. All the transducers and computational elements are analog circuits made with a conventional CMOS process.https://resolver.caltech.edu/CaltechAUTHORS:20151012-141538820Computing Motion Using Resistive Networks
https://resolver.caltech.edu/CaltechAUTHORS:20160107-154149599
Year: 1988
To us, and to other biological organisms, vision seems effortless. We open
our eyes and we "see" the world in all its color, brightness, and movement.
Yet, we have great difficulties when trying to endow our machines with similar
abilities. In this paper we shall describe recent developments in the theory of
early vision which lead from the formulation of the motion problem as an ill-posed
one to its solution by minimizing certain "cost" functions. These cost
or energy functions can be mapped onto simple analog and digital resistive
networks. Thus, we shall see how the optical flow can be computed by injecting
currents into resistive networks and recording the resulting stationary voltage
distribution at each node. These networks can be implemented in cMOS VLSI
circuits and represent plausible candidates for biological vision systems.https://resolver.caltech.edu/CaltechAUTHORS:20160107-154149599Analog VLSI for auditory and vision signal processing
https://resolver.caltech.edu/CaltechAUTHORS:20141222-112010277
Year: 1988
DOI: 10.1109/IEDM.1988.32736
Various issues connected with the use of analog VLSI for auditory and vision signal processing are discussed. Particular attention is given to the impact of CMOS integrated-circuit technology and precision, reliability and noise considerations.https://resolver.caltech.edu/CaltechAUTHORS:20141222-112010277A CMOS VLSI cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20141222-151200537
Year: 1988
DOI: 10.1109/ICASSP.1988.197063
An engineered system that hears, such as a speech recognizer, can be designed by modeling the cochlea, or inner ear, and higher levels of the auditory nervous system. To be useful in such a system, a model
of the cochlea should incorporate a variety of known effects, such as an asymmetric lowpass/bandpass response at each output channel, a short ringing time, and active adaptation to a wide range of input signal
levels. An analog electronic cochlea has been built in CMOS VLSI technology using micropower techniques to achieve this goal of usefulness via realism. The key point of the model and circuit is that a cascade of simple, nearly linear, second-order filter stages with controllable
Q parameters suffices to capture the physics of the fluid-dynamic traveling-wave system in the cochlea, including the effects of adaptation and active gain involving the outer hair cells. Measurements on the test
chip suggest that the circuit matches both the theory and observations from real cochleas.https://resolver.caltech.edu/CaltechAUTHORS:20141222-151200537Analog VLSI Models of Oscillatory Biological Neural Circuits
https://resolver.caltech.edu/CaltechAUTHORS:20150927-223445373
Year: 1989
We have used analog VLSI technology to model a class of biological neural circuits known as central pattern generators (CPGs). These circuits generate
rhythmic patterns of activity which drive motor behavior in animals. We have designed, fabricated, and tested a model neuron circuit that relies on many of the same mechanisms as a biological CPG neuron, and have shown
that this neuron can be used to build small models of known CPGs that produce patterns of output similar to the observed biological patterns.https://resolver.caltech.edu/CaltechAUTHORS:20150927-223445373Circuit Models of Sensory Transduction in the Cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20150918-160002977
Year: 1989
Nonlinear signal processing is an integral part of sensory transduction in
the nervous system. Sensory inputs are analog, continuous-time signals with a
large dynamic range, whereas central neurons encode information with limited
dynamic range and temporal specificity, using fixed-width, fixed-height pulses.
Sensory transduction uses nonlinear signal processing to reduce real-world input
to a neural representation, with a minimal loss of information.https://resolver.caltech.edu/CaltechAUTHORS:20150918-160002977Neural computation in analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150120-164428118
Year: 1989
DOI: 10.1109/ACSSC.1989.1200737
Neural systems found in the brains of even very simple animals are amazingly effective at performing computations on information arising in the natural world. Neural structures expend less than a millionth of the power required by our most advanced digital
signal processing technology for a similar task. At the level of a single device, however, our silicon technology can much more closely approach the energy requirements of structures in the brain. The nervous system achieves its remarkable effectiveness by using the fundamental device physics to define its computational primitives. In addition, algorithmic structures that emphasize
spatial locality make best use of limited wiring resources. A deeper understanding of the design approach used by neural systems may make possible a new, and very powerful, engineering discipline.https://resolver.caltech.edu/CaltechAUTHORS:20150120-164428118Winner-Take-All Networks of O(N) Complexity
https://resolver.caltech.edu/CaltechAUTHORS:20141212-145244773
Year: 1989
We have designed, fabricated, and tested a series of compact CMOS integrated circuits that realize the winner-take-all function. These analog, continuous-time circuits use only O(n) of interconnect to perform this function. We have also modified the winner-take-all circuit, realizing a circuit that computes local nonlinear inhibition.https://resolver.caltech.edu/CaltechAUTHORS:20141212-145244773Modeling Small Oscillating Biological Networks in Analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20141212-145236780
Year: 1989
We have used analog VLSI technology to model a class of small oscillating
biological neural circuits known as central pattern generators
(CPG). These circuits generate rhythmic patterns of activity
which drive locomotor behaviour in the animal. We have designed,
fabricated, and tested a model neuron circuit which relies on many
of the same mechanisms as a biological central pattern generator
neuron, such as delays and internal feedback. We show that this
neuron can be used to build several small circuits based on known
biological CPG circuits, and that these circuits produce patterns of
output which are very similar to the observed biological patterns.https://resolver.caltech.edu/CaltechAUTHORS:20141212-145236780An Electronic Photoreceptor Sensitive to Small Changes in Intensity
https://resolver.caltech.edu/CaltechAUTHORS:20141212-141111206
Year: 1989
We describe an electronic photoreceptor circuit that is sensitive to small changes in incident light intensity. The
sensitivity to changes in the intensity is achieved by feeding back to the input a filtered version of the output. The feedback loop includes a hysteretic element. The circuit
behaves in a manner reminiscent of the gain control properties and temporal responses of a variety of retinal cells, particularly retinal bipolar cells. We compare the thresholds for detection of intensity increments by a human and by the circuit. Both obey Weber's law and for both the temporal contrast sensitivities are nearly identical.https://resolver.caltech.edu/CaltechAUTHORS:20141212-141111206Silicon Models of Neural Computation
https://resolver.caltech.edu/CaltechAUTHORS:20150927-224418112
Year: 1989
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150927-224418112An Analog VLSI Model of Adaptation in the Vestibulo-Ocular Reflex
https://resolver.caltech.edu/CaltechAUTHORS:20150130-161640003
Year: 1990
The vestibulo-ocular reflex (VOR) is the primary mechanism that controls the compensatory eye movements that stabilize retinal images during rapid head motion. The primary pathways of this system are feed-forward, with inputs from the semicircular canals and outputs to the oculomotor system. Since visual feedback is not used directly in the VOR computation, the system must exploit motor learning to perform correctly. Lisberger(1988) has proposed
a model for adapting the VOR gain using image-slip information from the retina. We have designed and tested analog very large-scale integrated (VLSI) circuitry that implements a simplified version of Lisberger's adaptive VOR model.https://resolver.caltech.edu/CaltechAUTHORS:20150130-161640003An Analog Electronic Cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20141222-163913984
Year: 1990
An engineered system that hears, such as a speech recognizer, can be designed by modeling the cochlea, or inner ear, and higher levels of the auditory nervous system. To be useful in such a system, a model of the cochlea should incorporate a variety of known effects,
such as an asymmetric low-pass/bandpass response at each output channel, a short ringing time, and active adaptation to a wide range of input signal levels. An analog electronic cochlea has been built in CMOS
VLSI technology using micropower techniques to achieve this goal of usefulness via realism. The key point of the model and circuit is that a cascade of simple, nearly linear, second-order filter stages with controllable
Q parameters suffices to capture the physics of the fluid-dynamic traveling-wave system in the cochlea, including the effects of adaptation and active gain involving the outer hair cells. Measurements
on the test chip suggest that the circuit matches both the theory and observations from real cochleas.https://resolver.caltech.edu/CaltechAUTHORS:20141222-163913984A Silicon Model of Auditory Localization
https://resolver.caltech.edu/CaltechAUTHORS:20150109-124214444
Year: 1990
The principles of organization of neural systems arose
from the combination of the performance requirements
for survival and the physics of neural elements. From
this perspective, the extraction of time-domain information
from auditory data is a challenging computation;
the system must detect changes in the data which
occur in tens of microseconds, using neurons which can
fire only once per several milliseconds. Neural
approaches to this problem succeed by closely coupling
algorithms and implementation, unlike standard engineering
practice, which aims to define algorithms that
are easily abstracted from hardware implementation.https://resolver.caltech.edu/CaltechAUTHORS:20150109-124214444Fundamental transition in the electronic nature of solids
https://resolver.caltech.edu/CaltechAUTHORS:20210127-142447762
Year: 1990
DOI: 10.1007/978-94-009-0657-0_10
The fundamental electronic properties of non- metallic, inorganic, crystalline solids depend in a natural manner on the character of the chemical bond which is developed between constituent atoms. For example, the familiar Group-IV semiconductors are totally covalent and exhibit characteristics which are qualitatively different from highly ionic materials, such as the alkali halides. However, many materials of fundamental and practical importance are intermediate between these two extremes; it is not immediately evident how their properties may be treated. We will demonstrate here that if crystalline solids are ordered by some measure of their bond ionicity, then one finds striking evidence for a universal and surprisingly abrupt transition in many electronic properties associated with the quantum mechanical valence state. This transition divides crystalline solids into two well-defined classes: "covalent" and "ionic." Within each class there is a unifying character to the observed properties.https://resolver.caltech.edu/CaltechAUTHORS:20210127-142447762A Novel Associative Memory Implemented Using Collective Computation
https://resolver.caltech.edu/CaltechAUTHORS:20141223-104942966
Year: 1990
A radically new type of associative memory, the ASSOCMEM, has been implemented in VLSI and tested. Analog circuit techniques are used to construct a network that evolves towards fully restored (digital) fixed-points that are the memories of the system. Association occurs
on the whole source word, each bit of which may assume a continuous analog value. The network does not require the distinction of a search key from a data field in either the source or target words. A key may be dynamically defined by differentially weighting any subset of the source
word. The key need not be exact; the system will evolve to the closest memory. In the case when the key is the whole input word, the system may be thought of as performing error correction.https://resolver.caltech.edu/CaltechAUTHORS:20141223-104942966Auditory Processing Using Analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150112-144142710
Year: 1990
The architectures of animal nervous systems are shaped by evolution and
carried in the genetic code. The essential quality of such an architecture is
that it must learn from the environment in which the animal lives. The single
common element of learning is the time coincidence in the arrival of nerve
impulses. The arrival of one impulse or burst of impulses closely followed
by another is taken by the nervous system as evidence for a cause-and-effect
relationship between the two. The temporal structure of auditory stimuli
encodes far more information than standard engineering methods have ever
been able to extract. The fact that animal nervous systems can extract this
information leads to the conclusion that heretofore unexplored computational
paradigms are involved. The design of large-scale integrated circuits
employing a substantial fraction of analog processing is a promising
approach to this class of problems.https://resolver.caltech.edu/CaltechAUTHORS:20150112-144142710VLSI Implementation of Neural Networks
https://resolver.caltech.edu/CaltechAUTHORS:20150109-122323757
Year: 1990
The recent resurgence of interest in neural networks
(NNs) has resulted in the application of NNs to a
variety of problem domains. The initial results show
great promise, which in tum is motivating research in
appropriate implementation technologies. Several approaches
are now being explored; at one extreme of
the spectrum is algorithmic research for software running
on a conventional computer, whereas at the
other extreme researchers are exploring radically new
computational structures, such as optical computing.
A more conservative approach relies on adapting the
existing silicon-based CMOS VLSI (complementary
metal oxide semiconductor, very large scale integration)
technology to the unique needs of NN
computation.https://resolver.caltech.edu/CaltechAUTHORS:20150109-122323757A neuron-based pulse servo for motion control
https://resolver.caltech.edu/CaltechAUTHORS:20141222-120754146
Year: 1990
DOI: 10.1109/ROBOT.1990.126254
Sensory control based on biological computational
paradigms can be implemented using low-power
analog very large-scale integrated circuitry. We describe
a design frame and a set of circuit elements with which
generic motor controllers can be implemented. We then
embed a simple proportional-derivative motor controller
in the design frame, and describe its performance advantages
over a more traditional controller. We also discuss
the merits of biologically inspired systems used in applications related to robotics.https://resolver.caltech.edu/CaltechAUTHORS:20141222-120754146Time-derivative adaptive silicon photoreceptor array
https://resolver.caltech.edu/CaltechAUTHORS:20150227-114653482
Year: 1991
DOI: 10.1117/12.49323
We designed and tested a two-dimensional silicon receptor array constructed from pixels that temporally high-pass filter the incident image. There are no surround interactions in the array; all pixels operate independently except for their correlation due to the input image. The high- pass output signal is computed by sampling the output of an adaptive, high-gain, logarithmic photoreceptor during the scanout of the array. After a pixel is sampled, the output of the pixel is reset to a fixed value. An interesting capacitive coupling mechanism results in a controllable high-pass filtering operation. The resulting array has very low offsets. The computation that the array performs may be useful for time-domain image processing, for example, motion computation.https://resolver.caltech.edu/CaltechAUTHORS:20150227-114653482A Silicon Model of Early Visual Processing
https://resolver.caltech.edu/CaltechAUTHORS:20141223-110732666
Year: 1993
Many of the most striking phenomena known from perceptual
psychology are a direct result of the first levels of
neural processing. In the visual systems of higher animals,
the well-known center-surround response to local stimuli is
responsible for some of the strongest visual illusions. For
example, Mach bands, the Hermann-Hering grid illusion,
and the Craik-O'Brian-Comsweet illusion can all be traced
to simple inhibitory interactions between elements of the
retina (Ratliff 1965). The high degree to which a perceived
image is independent of the absolute illumination
level can be viewed as a property of the mechanism by
which incident light is transduced into an electrical signal.
We present a model of the first stages of retinal processing
in which these phenomena are viewed as natural
by-products of the mechanism by which the system
adapts to a wide range of viewing conditions. Our retinal
model is implemented as a single silicon chip, which contains
integrated photoreceptors and processing elements;
this chip generates, in real time, outputs that correspond
directly to signals observed in the corresponding levels of
biological retinas.https://resolver.caltech.edu/CaltechAUTHORS:20141223-110732666Adaptive Photoreceptor with Wide Dynamic Range
https://resolver.caltech.edu/CaltechAUTHORS:20150113-105738115
Year: 1994
DOI: 10.1109/ISCAS.1994.409266
We describe a photoreceptor circuit that can be used in massively parallel analog VLSI silicon chips, in conjunction
with other local circuits, to perform initial analog visual
information processing. The receptor provides a continuous-time output that has low gain for static signals (including circuit mismatches), and high gain for transient signals that are centered around the adaptation point. The response is logarithmic, which makes the response to a fixed image contrast invariant to absolute light intensity. The 5-transistor receptor can be fabricated in an area of about 70 μm by 70 μm in a 2-μm single-poly CMOS technology. It has a dynamic range of 1-2 decades at a single adaptation level, and a total dynamic range of more than 6 decades. Several technical improvements in the circuit yield an additional 1-2 decades dynamic range over previous designs without sacrificing signal quality. The lower limit of the dynamic range, defined arbitrarily as the illuminance at which the bandwidth of the
receptor is 60 Hz, is at approximately 1 lux, which is the border between rod and cone vision and also the limit of current consumer video cameras. The receptor uses an adaptive element that is resistant to excess minority carrier diffusion. The continuous and logarithmic transduction process makes the bandwidth scale with intensity. As a result, the total A.C.
RMS receptor noise is constant, independent of intensity.
The spectral density of the noise is within a factor of two of pure photon shot noise and varies inversely with intensity. The connection between shot and thermal noise in a system governed by Boltzman statistics is beautifully illustrated.https://resolver.caltech.edu/CaltechAUTHORS:20150113-105738115Continuous-time adaptive delay system
https://resolver.caltech.edu/CaltechAUTHORS:20150113-105207012
Year: 1994
DOI: 10.1109/ISCAS.1994.409212
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 μm CMOS technology are in agreement with the analysishttps://resolver.caltech.edu/CaltechAUTHORS:20150113-105207012A Silicon Axon
https://resolver.caltech.edu/CaltechAUTHORS:20150305-152221206
Year: 1995
We present a silicon model of an axon which shows promise as a building block for pulse-based neural computations involving correlations of pulses across both space and time. The circuit shares a number of features with its biological counterpart including an
excitation threshold, a brief refractory period after pulse completion, pulse amplitude restoration, and pulse width restoration. We provide a simple explanation of circuit operation and present data from a chip fabricated in a standard 2μm CMOS process through the MOS Implementation Service (MOSIS). We emphasize the necessity
of the restoration of the width of the pulse in time for stable propagation in axons.https://resolver.caltech.edu/CaltechAUTHORS:20150305-152221206Single Transistor Learning Synapses
https://resolver.caltech.edu/CaltechAUTHORS:20150305-153222850
Year: 1995
We describe single-transistor silicon synapses that compute, learn, and provide non-volatile memory retention. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and the weight value, and update the weight value according to a Hebbian or a backpropagation learning rule. Memory is accomplished via charge storage on polysilicon
floating gates, providing long-term retention without refresh. The synapses efficiently use the physics of silicon to perform weight updates; the weight value is increased using tunneling and the weight
value decreases using hot electron injection. The small size and low power operation of single transistor synapses allows the development of dense synaptic arrays. We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. When the steady state source current is used as
the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current. The synaptic array was fabricated in the standard 2μm double - poly, analog process available from MOSIS.https://resolver.caltech.edu/CaltechAUTHORS:20150305-153222850Single transistor learning synapse with long term storage
https://resolver.caltech.edu/CaltechAUTHORS:20150113-122333554
Year: 1995
DOI: 10.1109/ISCAS.1995.523729
We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectivity for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current.https://resolver.caltech.edu/CaltechAUTHORS:20150113-122333554A High-Resolution Non-Volatile Analog Memory Cell
https://resolver.caltech.edu/CaltechAUTHORS:20150113-150432993
Year: 1995
DOI: 10.1109/ISCAS.1995.523872
A 3-transistor non-volatile analog storage cell with 14 bits effective resolution and rail-to-rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hot-electron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feedback control, errors due to oxide mismatch or trapping can be nearly eliminated, Small size and low power consumption make the cell especially attractive for use in analog neural networks. The cell is fabricated in a 2 μm n-well silicon Bi-CMOS process available from MOSIS.https://resolver.caltech.edu/CaltechAUTHORS:20150113-150432993A νMOS soft-maximum current mirror
https://resolver.caltech.edu/CaltechAUTHORS:20150113-151535084
Year: 1995
DOI: 10.1109/ISCAS.1995.523876
In this paper, we describe a novel circuit consisting of N+1 MOS transistors and a single floating gate which computes a soft maximum of N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage swing and an interesting feedback mechanism which causes its output impedance to be comparable to that of a normal MOS transistor despite the fact that the output device is a floating-gate transistor.https://resolver.caltech.edu/CaltechAUTHORS:20150113-151535084An analog VLSI cochlea with new transconductance amplifiers and nonlinear gain control
https://resolver.caltech.edu/CaltechAUTHORS:20150113-155313873
Year: 1996
DOI: 10.1109/ISCAS.1996.541591
We show data from a working 45-stage analog VLSI cochlea, built on a 2.2 mm×2.2 mm tiny chip. The novel architectural features in this cochlea are: (1) The use of a wide-linear-range low-noise subthreshold transconductance amplifier. (2) The use of "fuse-like" nonlinear positive-feedback amplification in the second-order cochlear filter. Several new circuit techniques used in the design are described here. The fuse nonlinearity shuts off the positive-feedback amplification at large signal levels instead of merely saturating it, like in prior designs, and leads to increased adaptation and improved large-signal stability in the filter. The fuse filter implements a functional model of gain control due to outer hair cells in the biological cochlea. We present data for travelling-wave patterns in our silicon cochlea that reproduce linear and nonlinear effects in the biological cochlea.https://resolver.caltech.edu/CaltechAUTHORS:20150113-155313873Nonvolatile correction of Q-offsets and instabilities in cochlear filters
https://resolver.caltech.edu/CaltechAUTHORS:20150113-160204726
Year: 1996
DOI: 10.1109/ISCAS.1996.541600
We present a feedback circuit that performs nonvolatile correction of instabilities and resonant-gain offsets (Q-offsets) in individual cochlear filters. The subthreshold CMOS circuit adapts using analog floating-gate technology. We present experimental data from a working chip that illustrates the performance of the circuit. We discuss how to extend our work to do very long-term gain control in the silicon cochlea. Positive-feedback circuits, such as our cochlear filters, are very sensitive to parameter variations. This potential problem becomes an advantage in our corrective feedback loop where the hypersensitivity behaves merely like high loop gain.https://resolver.caltech.edu/CaltechAUTHORS:20150113-160204726An autozeroing amplifier using PFET hot-electron injection
https://resolver.caltech.edu/CaltechAUTHORS:20150113-155800936
Year: 1996
DOI: 10.1109/ISCAS.1996.541599
We have developed an amplifier which removes its "off-set" as a natural part of its operation by modifying the charge on a floating gate. The charge on the floating gate is adapted by a combination of electron tunneling and hot-electron injection, resulting in a nonlinear high-pass filter with a cutoff frequency less than 1 Hz. We show experimental data from this autozeroing amplifier for various input waveforms, and an analytical model which fits the output waveforms. This autozeroing amplifier is a single-input case of a continuous learning circuit.https://resolver.caltech.edu/CaltechAUTHORS:20150113-155800936The matching of small capacitors for analog VLSI
https://resolver.caltech.edu/CaltechAUTHORS:20150113-154605832
Year: 1996
DOI: 10.1109/ISCAS.1996.539873
The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 μm×6 μm to 20 μm×20 μm fabricated in a standard 2 μm double-poly CMOS process available through MOSIS. For a size of 6 μm×6 μm, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 μm×20 μm size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching.https://resolver.caltech.edu/CaltechAUTHORS:20150113-154605832A High Resolution CMOS Imager With Active Pixel Using Capacitively Coupled Bipolar Operation
https://resolver.caltech.edu/CaltechAUTHORS:20150113-161240691
Year: 1997
DOI: 10.1109/VTSA.1997.614727
The active pixel sensor technology promises high
performance than conventional CCD imagers. This paper
reports a new high resolution CMOS imager with one
transistor active pixel sensing based on capacitor-coupled
bipolar action. The base capacitor is pulsed negatively for
image integration and positively for image sensing. The pixel size is 5.9um x 5.9um (on 0.8um design rule). The prototype imager has an array of 480 x 640 and operating at 5v Vcc. This active pixel structure is promising for future high-performance and high-density imagers in the information highway era.https://resolver.caltech.edu/CaltechAUTHORS:20150113-161240691A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea
https://resolver.caltech.edu/CaltechAUTHORS:20150112-105156628
Year: 1998
In this paper we describe a cochlea that attains a dynamic range of 6ldB at the BF of a typical cochlear stage by using four techniques:
1. The previously described WLR
2. A low-noise second-order filter topology
3. Dynamic gain control (AGC)
4. The architecture of overlapping cochlear cascades
In addition, we use three techniques that ensure the presence of a robust infrastructure
in the cochlea:
l. Automatic offset-compensation circuitry in each cochlear filter prevents offset accumulation along the cochlea.
2. Cascode circuitry in the WLRs increase the latter's DC gain, and prevent low-frequency signal attenuation in the cochlea.
3. Translinear bipolar biasing circuits provide Qs that are approximately invariant with corner frequency, and allow better matching. Bipolar biasing circuits were first used in cochlear designs by [32].
We shall discuss all of these preceding techniques in this paper.https://resolver.caltech.edu/CaltechAUTHORS:20150112-105156628Floating-Gate MOS Synapse Transistors
https://resolver.caltech.edu/CaltechAUTHORS:20150109-144208064
Year: 1998
DOI: 10.1007/978-0-585-28001-1_14
Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile
analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices,
such as EEPROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate
transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si0_2, these devices have not seen wide use as memory elements in silicon learning systems.https://resolver.caltech.edu/CaltechAUTHORS:20150109-144208064A Low-Power Wide-Linear-Range Transconductive Amplifier
https://resolver.caltech.edu/CaltechAUTHORS:20150112-105932717
Year: 1998
In the past few years, engineers have improved the linearity of MOS transconductor
circuits 12, 5, 10, 11, 19, 20, 26, 28, 29, 32]. These advances have been primarily
in the area of above-threshold, high-power, high-frequency, continuous-time
filters. Although it is possible to implement auditory filters (20Hz- 20khz)
with these techniques, it is inefficient to do so. The transconductance and current
levels in above-threshold operation are so high that large capacitances or
transistors with very low W / L are required to create low-frequency poles, and
area and power are wasted. In addition, it is difficult to span 3 orders of magnitude
of transconductance with a square law, unless we use transistors with
ungainly aspect ratios. However, it is easy to obtain a wide linear range above
threshold.https://resolver.caltech.edu/CaltechAUTHORS:20150112-105932717Feynman as a colleague
https://resolver.caltech.edu/CaltechAUTHORS:20150109-111939447
Year: 1999
Feynman and I both arrived at Caltech in 1952 - he as a new professor of physics, and I as a freshman undergraduate. My passionate interest was electronics, and I avidly consumed any material I could find on the subject: courses, seminars,
books, etc. As a consequence, I was dragged through several versions of standard electromagnetic theory: E and B, D and H, curls of curls, the whole nine yards.
The only bright light in the subject was the vector potential, to which I was always attracted because, somehow, it made sense to me. It seemed a shame that the
courses I attended didn't make more use of it. In my junior year, I took a course in mathematical physics from Feynman - what a treat. This man could think conceptually about physics, not just regurgitate dry formalism. After one quarter of Feynman, the class was spoiled for any other professor. But when we looked at the registration form for the next quarter, we found Feynman as teaching high-energy
physics, instead of our course. Bad luck! When our first class met, however, here came Feynman. "So you're not teaching high-energy physics?" I asked. "No" he replied, "low-energy mathematics." Feynman liked the vector potential too; for him it was the link between electromagnetism and quantum mechanics. As he put it
"In the general theory of quantum electrodynamics, one takes the vector and scalar potentials as fundamental quantities in a set of equations that replace the Maxwell
equations." I learned enough about it from him to know that, some day, I wanted to do all of electromagnetic theory that way.https://resolver.caltech.edu/CaltechAUTHORS:20150109-111939447Life Without Bits
https://resolver.caltech.edu/CaltechAUTHORS:20150112-152455731
Year: 1999
[no abstract]https://resolver.caltech.edu/CaltechAUTHORS:20150112-152455731Scaling of MOS Technology to Submicrometer Feature Sizes
https://resolver.caltech.edu/CaltechAUTHORS:20150109-120856432
Year: 1999
Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion
of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other
technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology
is reduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at the
system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude
with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.https://resolver.caltech.edu/CaltechAUTHORS:20150109-120856432A Bidirectional Analog VLSI Cochlear Model
https://resolver.caltech.edu/CaltechAUTHORS:20150112-115633935
Year: 1999
A novel circuit is presented for implementing a bidirectional passive cochlear
model in analog VLSI. The circuit includes a subcircuit for modelling the
fluid in the cochlear duct, and a subcircuit for modelling the passive basilar
membrane. The circuit is compared to the classical 1-D transmission
line cochlear model and found to be equivalent. The approach leads to
an unexpected fa.ult tolerance in the form of insensitivity to transconductance
amplifier offset voltages. A 545-stage cochlea has been fabricated and
demonstrates the expected wave propagation behaviour.https://resolver.caltech.edu/CaltechAUTHORS:20150112-115633935Collective Electrodynamics I
https://resolver.caltech.edu/CaltechAUTHORS:20150109-113726556
Year: 1999
Standard results of electromagnetic theory are derived from the direct interaction of macroscopic quantum systems; the only assumptions used are the Einstein-deBroglie
relations, the discrete nature of charge, the Green's function for the vector potential, and the continuity of the wave function. No reference is needed to
Maxwell's equations or to traditional quantum formalism. Correspondence limits based on classical mechanics are shown to be inappropriate.https://resolver.caltech.edu/CaltechAUTHORS:20150109-113726556The Evolution of Electronic Photography
https://resolver.caltech.edu/CaltechAUTHORS:20150112-110810021
Year: 2001
Silver-based photography was invented in the mid-1800s,
and has existed in its modem form for over 100 years.
More than 60 million film cameras will be sold this year, a
larger number than for any previous year. In spite of the
explosion in digital technology for other applications,
digital camera technology still produces images that arc
vastly inferior to film images. Recent developments in
silicon image sensors have made possible the direct capture
of images that exceed the quality of film images.
Over the next decade, cameras based on these
principles will supplant film cameras in nearly all
applications. In many ways, electronic photography has
gone through evolutionary steps closely paralleling those
experienced in the early days of film photography. The
current leading-edge technology will be discussed, with
referenced to its place in the evolutionary sequence.https://resolver.caltech.edu/CaltechAUTHORS:20150112-110810021Neuromorphic Engineering: Overview and Potential
https://resolver.caltech.edu/CaltechAUTHORS:20150126-165023417
Year: 2005
DOI: 10.1109/IJCNN.2005.1556463
It is evident to even the most casual observer that the
nervous systems of animals are able to accomplish feats
that cannot be approached by our most powerful
computing systems. Given the exponential increase in
computing power over the last 45 years, our inability to
rival the common housefly has become downright
embarrassing. What is going on?https://resolver.caltech.edu/CaltechAUTHORS:20150126-165023417The evolution of technology
https://resolver.caltech.edu/CaltechAUTHORS:20150127-163653667
Year: 2013
DOI: 10.1109/ISSCC.2013.6487621
Faraday's Law of induction gave us generators, motors, telegraph, telephone, etc. The vacuum tube gave us long-distance telephone, radio, hi-fi audio, television, and early computers. Microcircuits have given us personal computers, cell phones, the Internet, and GPS positioning.
Now, What?https://resolver.caltech.edu/CaltechAUTHORS:20150127-163653667The Nature of Light: What are "Photons"?
https://resolver.caltech.edu/CaltechAUTHORS:20131209-074730086
Year: 2013
DOI: 10.1117/12.2046381
We are told that our present understanding of physical law was ushered in by the Quantum Revolution, which began around 1900 and was brought to fruition around 1930 with the formulation of modern Quantum Mechanics. The "photon" was supposed to be the centerpiece of this revolution, conveying much of its conceptual flavor. What happened during that period was a rather violent redirection of the prevailing world view in and around physics - a process that has still not settled. In this paper I critically review the evolution of the concepts involved, from the time of Maxwell up to the present day. At any given time, discussions in and around any given topic take place using a language that presupposes a world view or zeitgeist. The world view itself limits what ideas are expressible. We are all prisoners of the language we have created to develop our understanding to its present state. Thus the very concepts and ways of thinking that have led to progress in the past are often the source of blind spots that prevent progress into the future. The most insidious property of the world view at any point in time is that it involves assumptions that are not stated. In what follows we will have a number of occasions to point out the assumptions in the current world view, and to develop a new world view based on a quite different set of assumptions.https://resolver.caltech.edu/CaltechAUTHORS:20131209-074730086My Early Collaboration with Bill Goddard
https://resolver.caltech.edu/CaltechAUTHORS:20210127-082657092
Year: 2021
DOI: 10.1007/978-3-030-18778-1_3
In 1962, I struck up a collaboration with Bill Goddard and several solid-state physics labs to do a systematic study of the properties of metal-semiconductor junctions. These structures are ubiquitous in semiconductor devices and are central to their operation. Understanding them is at the boundary of Physics and Chemistry.https://resolver.caltech.edu/CaltechAUTHORS:20210127-082657092Symmetry, Transactions, and the Mechanism of Wave Function Collapse
https://resolver.caltech.edu/CaltechAUTHORS:20220114-163105179
Year: 2022
DOI: 10.3390/books978-3-0365-2695-9
The Transactional Interpretation of quantum mechanics exploits the intrinsic time-symmetry of wave mechanics to interpret the ψ and ψ* wave functions present in all wave mechanics calculations as representing retarded and advanced waves moving in opposite time directions that form a quantum "handshake" or transaction. This handshake is a 4D standing-wave that builds up across space-time to transfer the conserved quantities of energy, momentum, and angular momentum in an interaction. Here, we derive a two-atom quantum formalism describing a transaction. We show that the bi-directional electromagnetic coupling between atoms can be factored into a matched pair of vector potential Green's functions: one retarded and one advanced, and that this combination uniquely enforces the conservation of energy in a transaction. Thus factored, the single-electron wave functions of electromagnetically-coupled atoms can be analyzed using Schrödinger's original wave mechanics. The technique generalizes to any number of electromagnetically coupled single-electron states—no higher-dimensional space is needed. Using this technique, we show a worked example of the transfer of energy from a hydrogen atom in an excited state to a nearby hydrogen atom in its ground state. It is seen that the initial exchange creates a dynamically unstable situation that avalanches to the completed transaction, demonstrating that wave function collapse, considered mysterious in the literature, can be implemented with solutions of Schrödinger's original wave mechanics, coupled by this unique combination of retarded/advanced vector potentials, without the introduction of any additional mechanism or formalism. We also analyze a simplified version of the photon-splitting and Freedman–Clauser three-electron experiments and show that their results can be predicted by this formalism.https://resolver.caltech.edu/CaltechAUTHORS:20220114-163105179