[ { "id": "authors:92yk4-35643", "collection": "authors", "collection_id": "92yk4-35643", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140206-111915844", "type": "monograph", "title": "25 Years Ago: The First Asynchronous Microprocessor", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "Twenty-five years ago, in December 1988, my\nresearch group at Caltech submitted the world's\nfirst asynchronous (\"clockless\") microprocessor\ndesign for fabrication to MOSIS. We received\nthe chips in early 1989; testing started in February 1989. The chips were found fully functional on first silicon. The results were presented at the Decennial Caltech VLSI Conference in March of the same year. The first entirely\nasynchronous microprocessor had been designed\nand successfully fabricated. As the technology finally reaches industry, and with the benefit of a\nquarter-century hindsight, here is a recollection\nof this landmark project.", "doi": "10.7907/Z9QR4V3H", "publisher": "California Institute of Technology", "publication_date": "2014-01-27" }, { "id": "authors:1f4c9-16z49", "collection": "authors", "collection_id": "1f4c9-16z49", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20141125-133400175", "type": "monograph", "title": "Quantifying Near-Threshold CMOS Circuit Robustness", "author": [ { "family_name": "Keller", "given_name": "Sean", "clpid": "Keller-S" }, { "family_name": "Bhargav", "given_name": "Siddharth S.", "clpid": "Bhargav-S-S" }, { "family_name": "Moore", "given_name": "Chris", "clpid": "Moore-Chris" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "In order to build energy efficient digital CMOS circuits, the supply voltage must be reduced to near-threshold.\nProblematically, due to random parameter variation, supply\nscaling reduces circuit robustness to noise. Moreover, the effects of parameter variation worsen as device dimensions diminish, further reducing robustness, and making parameter variation one of the most significant hurdles to continued CMOS scaling. This paper presents a new metric to quantify circuit robustness with respect to variation and noise along with an efficient method of calculation. The method relies on the statistical analysis of standard cells and memories resulting an an extremely compact representation of robustness data. With this metric and method of\ncalculation, circuit robustness can be included alongside energy, delay, and area during circuit design and optimization.", "doi": "10.7907/Z9M043CG", "publisher": "California Institute of Technology", "publication_date": "2014" }, { "id": "authors:3b063-ca817", "collection": "authors", "collection_id": "3b063-ca817", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:2003.006a", "type": "monograph", "title": "An Architecture for Asynchronous FPGAs", "author": [ { "family_name": "Wong", "given_name": "Catherine G.", "clpid": "Wong-Catherine-G" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Thomas", "given_name": "Peter", "clpid": "Thomas-P" } ], "abstract": "We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.", "publisher": "Proceedings of the IEEE International Conference on Field-Programmable Technology, 2003", "publication_date": "2003-01-01" }, { "id": "authors:fbe8p-27d82", "collection": "authors", "collection_id": "fbe8p-27d82", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:2003.006", "type": "monograph", "title": "An Architecture for Asynchronous FPGAs", "author": [ { "family_name": "Wong", "given_name": "Catherine G.", "clpid": "Wong-Catherine-G" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Thomas", "given_name": "Peter", "clpid": "Thomas-P" } ], "abstract": "We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.", "doi": "10.7907/Z9X9288B", "publisher": "California Institute of Technology", "publication_date": "2003-01-01" }, { "id": "authors:pqps5-hr425", "collection": "authors", "collection_id": "pqps5-hr425", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:2002.003", "type": "monograph", "title": "Transistor Sizing of Energy-Delay-Efficient Circuits", "author": [ { "family_name": "P\u00e9nzes", "given_name": "Paul I.", "clpid": "P\u00e9nzes-P-I" }, { "family_name": "Nystr\u00f6em", "given_name": "Mika", "clpid": "Nystr\u00f6em-M" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, \ni.e., for optimal Et^n where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay. We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency.", "doi": "10.7907/Z9ZG6Q7T", "publisher": "California Institute of Technology", "publication_date": "2002-01-01" }, { "id": "authors:9wccf-45n08", "collection": "authors", "collection_id": "9wccf-45n08", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:2001.012", "type": "monograph", "title": "Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Nystr\u00f6m", "given_name": "Mika", "clpid": "Nystr\u00f6m-M" }, { "family_name": "Penzes", "given_name": "Paul", "clpid": "Penzes-P-I" }, { "family_name": "Wong", "given_name": "Catherine", "clpid": "Wong-Catherine-G" } ], "abstract": "This paper presents the speed and energy figures for an asynchronous implementation of a MIPS R3000 microprocessor. The design is almost entirely QDI and introduces a new fine-grained pipeline. The performance figures show that this design is four times as efficient as equivalent clocked designs and that its cycle time in FO4 units compares to that of high-performance dynamic pipelines.", "doi": "10.7907/Z99S1P11", "publisher": "California Institute of Technology", "publication_date": "2001-06-22" }, { "id": "authors:z0965-w7h55", "collection": "authors", "collection_id": "z0965-w7h55", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:2002.002", "type": "monograph", "title": "Global and local properties of asynchronous circuits optimized for energy efficiency", "author": [ { "family_name": "P\u00e9nzes", "given_name": "Paul I.", "clpid": "P\u00e9nzes-P-I" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "In this paper we explore global and local properties of asynchronous circuits sized for the energy efficiency metric Et^2. We develop a theory that enables an abstract view on transistor sizing. These results allow us to accurately estimate circuit performance and compare circuit design choices at logic gate level without going through the costly sizing process. We estimate that the improvement in energy efficiency due to sizing is 2 to 3.5 times when compared to a design optimized for speed.", "doi": "10.7907/Z9FJ2DSS", "publisher": "California Institute of Technology", "publication_date": "2001-01-01" }, { "id": "authors:45xh6-yv235", "collection": "authors", "collection_id": "45xh6-yv235", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:2001.007", "type": "monograph", "title": "ET^2: A Metric For Time and Energy Efficiency of Computation", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Nystr\u00f6em", "given_name": "Mika", "clpid": "Nystr\u00f6em-M" }, { "family_name": "Penzes", "given_name": "Paul", "clpid": "Penzes-P" } ], "contributor": [ { "family_name": "Melhem", "given_name": "Rami" }, { "family_name": "Graybill", "given_name": "Robert" } ], "abstract": "We investigate an efficiency metric for VLSI computation that includes energy, E, and time, t, in the form E t^2. We apply the metric to CMOS circuits operating outside velocity saturation when energy and delay can be exchanged\nby adjusting the supply voltage; we prove that under these assumptions, optimal Et^2 implies optimal energy and delay. We give experimental and simulation evidences of the range and limits of the assumptions. We derive\nseveral results about sequential, parallel, and pipelined computations optimized for E t^2, including a result about the optimal length of a pipeline. We discuss transistor sizing for optimal Et^2 and show that, for fixed, nonzero execution rates, the optimum is achieved when the sum of the transistor-gate capacitances is twice the sum of the parasitic capacitances-not for minimum transistor sizes. We derive an approximation for E t^n (for arbitrary n) of an optimally sized system that can be computed without actually sizing the transistors; we show that this approximation is accurate. We prove that when multiple, adjustable supply voltages are allowed, the optimal Et^2 for the sequential composition of components is achieved when the supply voltages are adjusted so that the components consume equal power. Finally, we give rules for computing the Et^2 of the sequential and parallel compositions of systems, when the Et^2 of the components are known.", "doi": "10.7907/Z9K935JZ", "publisher": "California Institute of Technology", "publication_date": "2001-01-01" }, { "id": "authors:xpnkr-fdn96", "collection": "authors", "collection_id": "xpnkr-fdn96", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1995.cs-tr-95-11", "type": "monograph", "title": "Quasi-Delay-Insensitive Circuits are Turing-Complete", "author": [ { "family_name": "Manohar", "given_name": "Rajit", "clpid": "Manohar-R" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "Quasi-delay-insensitive (QDI) circuits are those whose correct operation does not depend on the delays of operators or wires, except for certain wires that form isochronic forks. In this paper we show that quasi-delay-insensitivity, stability and noninterference, and strong confluence are equivalent properties of a computation. In particular, this shows that QDI computations are deterministic. We show that the class of Turing-computable functions have QDI implementations by constructing a QDI Turing machine.", "doi": "10.7907/Z9H70CV1", "publisher": "California Institute of Technology", "publication_date": "1995-11-17" }, { "id": "authors:qbwq7-qze43", "collection": "authors", "collection_id": "qbwq7-qze43", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1994.cs-tr-94-21", "type": "monograph", "title": "Low-Energy Asynchronous Memory Design", "author": [ { "family_name": "Tierno", "given_name": "Jose A.", "clpid": "Tierno-J-A" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "We introduce the concept of energy per operation as a measure of performance of an asynchronous circuit. We show how to model energy consumption based on the high-level language specification. This model is independent of voltage and timing considerations. We apply this model to memory design. We show first how to dimension a memory array, and how to break up this memory array into smaller arrays to minimize the energy per access. We then show how to use cache memory and pre-fetch mechanisms to further reduce energy per access.", "doi": "10.7907/Z9X9289S", "publisher": "California Institute of Technology", "publication_date": "1994" }, { "id": "authors:z2zy9-d2m55", "collection": "authors", "collection_id": "z2zy9-d2m55", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1993.cs-tr-93-37", "type": "monograph", "title": "Submicron Systems Architecture: Semiannual Technical Report", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Van de Snepscheut", "given_name": "Jan L. A.", "clpid": "Van-de-Snepscheut-J-L-A" } ], "abstract": "[No abstract]", "doi": "10.7907/Z9NS0RX7", "publisher": "California Institute of Technology", "publication_date": "1993-11-01" }, { "id": "authors:4fh9g-yr824", "collection": "authors", "collection_id": "4fh9g-yr824", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1993.cs-tr-93-10", "type": "monograph", "title": "Submicron Systems Architecture", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Van de Snepscheut", "given_name": "Jan L. A.", "clpid": "Van-de-Snepscheut-J-L-A" } ], "abstract": "The first attachment to this report, a paper titled \"The Design of the Caltech Mosaic C\nMulticomputer,\" appeared in the March 1993 proceedings of the University of Washington\nSymposium on Integrated Systems. This paper describes the architecture, design, and\nprogramming of the Mosaic C multicomputer, and the status of the project as of December\n1992.\n\nThe following sections supplement the detailed information in this paper with reports on\nother and subsequent Mosaic-project activities and results. In addition, research efforts that\nare using the prototype Mosaic multicomputers for programming experiments are described\nin sections 3.1, 3.2, and 3.4.", "doi": "10.7907/4fh9g-yr824", "publisher": "California Institute of Technology", "publication_date": "1993-04-01" }, { "id": "authors:sq381-7zg42", "collection": "authors", "collection_id": "sq381-7zg42", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1993.cs-tr-93-38", "type": "monograph", "title": "An Asynchronous Microprocessor in Gallium Arsenide", "author": [ { "family_name": "Tierno", "given_name": "Jose A.", "clpid": "Tierno-J-A" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Borkovic", "given_name": "Drazen", "clpid": "Borkovic-D" }, { "family_name": "Lee", "given_name": "Tak Kwan", "clpid": "Lee-Tae-Kwan" } ], "abstract": "In this paper, several techniques for designing asynchronous circuits in Gallium Arsenide are presented. Several new circuits were designed, to implement specific functions necessary to the design of a full microprocessor. A sense-amplifier, a completion tree, and a general circuit structure for operators specified by production rules are introduced. These circuit were used and tested in a variety of designs, including two asynchronous microprocessors and two asynchronous static RAM's. One of the microprocessor runs at over 100 MIPS with a power consumption of 2 Watts.", "doi": "10.7907/Z9BC3WJ5", "publisher": "California Institute of Technology", "publication_date": "1993-01-01" }, { "id": "authors:5qr64-pv618", "collection": "authors", "collection_id": "5qr64-pv618", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1993.cs-tr-93-26", "type": "monograph", "title": "Tomorrow's Digital Hardware will be Asynchronous and Verified", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "Encouraged by the results of almost a decade of research and experimentation, we claim that tomorrow's design methods for digital VLSI will be based on a concurrent programming approach to high-level synthesis, asynchronous techniques, and correctness-preserving program transformations.", "doi": "10.7907/Z9125QPR", "publisher": "California Institute of Technology", "publication_date": "1993" }, { "id": "authors:tsdze-hh773", "collection": "authors", "collection_id": "tsdze-hh773", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1992.cs-tr-92-17", "type": "monograph", "title": "Submicron Systems Architecture Project : Semiannual Technical Report, 1 July 1992", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Van de Snepscheut", "given_name": "Jan L. A.", "clpid": "Van-de-Snepscheut-J-L-A" } ], "abstract": "The Mosaic C is an experimental fine-grain multicomputer\nbased on single-chip nodes. The Mosaic C chip includes 64KB of fast dynamic RAM,\nprocessor, packet interface, ROM for bootstrap and self-test, and a two-dimensional selftimed\nrouter. The chip architecture provides low-overhead and low-latency handling of\nmessage packets, and high memory and network bandwidth. Sixty-four Mosaic chips are\npackaged by tape-automated bonding (TAB) in an 8 x 8 array on circuit boards that can, in\nturn, be arrayed in two dimensions to build arbitrarily large machines. These 8 x 8 boards are\nnow in prototype production under a subcontract with Hewlett-Packard. We are planning\nto construct a 16K-node Mosaic C system from 256 of these boards. The suite of Mosaic\nC hardware also includes host-interface boards and high-speed communication cables. The\nhardware developments and activities of the past eight months are described in section 2.1.\nThe programming system that we are developing for the Mosaic C is based on the\nsame message-passing, reactive-process, computational model that we have used with earlier\nmulticomputers, but the model is implemented for the Mosaic in a way that supports finegrain\nconcurrency. A process executes only in response to receiving a message, and may in\nexecution send messages, create new processes, and modify its persistent variables before\nit either exits or becomes dormant in preparation for receiving another message. These\ncomputations are expressed in an object-oriented programming notation, a derivative of\nC++ called C+-. The computational model and the C+- programming notation are\ndescribed in section 2.2. The Mosaic C runtime system, which is written in C+-, provides\nautomatic process placement and highly distributed management of system resources. The\nMosaic C runtime system is described in section 2.3.", "doi": "10.7907/Z9WS8RF5", "publisher": "California Institute of Technology", "publication_date": "1992-07-01" }, { "id": "authors:tw7j6-a3r29", "collection": "authors", "collection_id": "tw7j6-a3r29", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1992.cs-tr-92-03", "type": "monograph", "title": "Delay-Insensitive Multiply-Accumulate Unit", "author": [ { "family_name": "Nielsen", "given_name": "Christian D.", "clpid": "Nielsen-C-D" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "[No abstract]", "doi": "10.7907/Z9MG7MPP", "publisher": "California Institute of Technology", "publication_date": "1992-01-01" }, { "id": "authors:b9wzv-xrc02", "collection": "authors", "collection_id": "b9wzv-xrc02", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-93-28", "type": "monograph", "title": "Synthesis of Asynchronous VLSI Circuits", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/b9wzv-xrc02", "publisher": "California Institute of Technology", "publication_date": "1991-01-01" }, { "id": "authors:j14fv-twh92", "collection": "authors", "collection_id": "j14fv-twh92", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-91-08", "type": "monograph", "title": "Asynchronous Datapaths and the Design of an Asynchronous Adder", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "This paper presents a general method for designing delay insensitive datapath circuits. Its emphasis is on the formal derivation of a circuit from its specification. We discuss the properties required in a code that is used to transmit data asynchronously, and we introduce such a code. We introduce a general method (in the form of a theorem) for distributing the evaluation of a function over a number of concurrent cells. This method requires that the code be \"distributive.\" We apply the method to the familiar example of a ripple-carry adder, and we give a CMOS implementation of the adder.", "doi": "10.7907/j14fv-twh92", "publisher": "California Institute of Technology", "publication_date": "1991-01-01" }, { "id": "authors:8274b-29b89", "collection": "authors", "collection_id": "8274b-29b89", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1990.cs-tr-90-17", "type": "monograph", "title": "Testing Delay-Insensitive Circuits", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Hazewindus", "given_name": "Pieter J.", "clpid": "Hazewindus-P-J" } ], "abstract": "We show that a single stuck-at fault in a non-redundant delay-insensitive circuit results in a transition either not taking place or firing prematurely, or both, during an execution of the circuit. A transition not taking place can be tested easily, as this always prevents a transition on a primary output from taking place. A premature firing can also be tested but the addition of testing points may be required to enforce the premature firing and to propagate the transition to a primary output. Hence all single stuck-at faults are testable. All test sequences can be generated from the high-level specification of the circuit. The circuits are hazard-free in normal operation and during the tests.", "doi": "10.7907/8274b-29b89", "publisher": "California Institute of Technology", "publication_date": "1990-01-01" }, { "id": "authors:47710-bts58", "collection": "authors", "collection_id": "47710-bts58", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1990.cs-tr-90-09", "type": "monograph", "title": "Asynchronous Circuits for Token-Ring Mutual Exclusion", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/47710-bts58", "publisher": "California Institute of Technology", "publication_date": "1990-01-01" }, { "id": "authors:gwkvs-p4122", "collection": "authors", "collection_id": "gwkvs-p4122", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1990.cs-tr-90-02", "type": "monograph", "title": "Limitations to Delay-Insensitivity in Asynchronous Circuits", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/gwkvs-p4122", "publisher": "California Institute of Technology", "publication_date": "1990-01-01" }, { "id": "authors:b11q2-j0d17", "collection": "authors", "collection_id": "b11q2-j0d17", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1990.cs-tr-90-18", "type": "monograph", "title": "Performance Analysis and Optimization of Asynchronous Circuits", "author": [ { "family_name": "Burns", "given_name": "Steven M.", "clpid": "Burns-S-M" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "We present a method for analyzing the time performance of asynchronous circuits, in paxticulax, those derived by program transformation from concurrent programs using the synthesis approach developed by the second author. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Such a metric provides a quantitative means by which to compare competing designs. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits-including those produced by using our synthesis method-these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization.", "doi": "10.7907/b11q2-j0d17", "publisher": "California Institute of Technology", "publication_date": "1990-01-01" }, { "id": "authors:bsky8-c6128", "collection": "authors", "collection_id": "bsky8-c6128", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1989.cs-tr-89-06", "type": "monograph", "title": "The First Aysnchronous Microprocessor: The Test Results", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Burns", "given_name": "Steven M.", "clpid": "Burns-S-M" }, { "family_name": "Lee", "given_name": "T. K.", "clpid": "Lee-T-K" }, { "family_name": "Borkovic", "given_name": "Drazen", "clpid": "Borkovic-D" }, { "family_name": "Hazewindus", "given_name": "Pieter J.", "clpid": "Hazewindus-P-J" } ], "abstract": "No abstract available.", "doi": "10.7907/bsky8-c6128", "publisher": "California Institute of Technology", "publication_date": "1989-01-01" }, { "id": "authors:zmy86-a1w29", "collection": "authors", "collection_id": "zmy86-a1w29", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1989.cs-tr-89-01", "type": "monograph", "title": "Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No Abstract.", "doi": "10.7907/zmy86-a1w29", "publisher": "California Institute of Technology", "publication_date": "1989-01-01" }, { "id": "authors:avec3-s7f02", "collection": "authors", "collection_id": "avec3-s7f02", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1989.cs-tr-89-02", "type": "monograph", "title": "The Design of an Asynchronous Microprocessor", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/avec3-s7f02", "publisher": "California Institute of Technology", "publication_date": "1989-01-01" }, { "id": "authors:zaevr-tmm71", "collection": "authors", "collection_id": "zaevr-tmm71", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1989.cs-tr-90-06", "type": "monograph", "title": "Distributed Sorting", "author": [ { "family_name": "Hofstee", "given_name": "H. Peter", "clpid": "Hofstee-H-P" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Van de Snepscheut", "given_name": "Jan L. A.", "clpid": "Van-de-Snepscheut-J-L-A" } ], "abstract": "In this paper we present a distributed sorting algorithm, which is a variation on exchange sort, i.e.,\nneighboring elements that are out of order are exchanged. We derive the algorithm by transforming a\nsequential algorithm into a distributed one. The transformation is guided by the distribution of the data\nover processes. First we discuss the case of two processes, and then the general case of one or more\nprocesses. Finally we propose a more efficient solution for the general case.", "doi": "10.7907/zaevr-tmm71", "publisher": "California Institute of Technology", "publication_date": "1989" }, { "id": "authors:585wz-fra78", "collection": "authors", "collection_id": "585wz-fra78", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1988.cs-tr-88-14", "type": "monograph", "title": "Syntax-Directed Translation of Concurrent Programs into Self-Timed Circuits", "author": [ { "family_name": "Burns", "given_name": "Steven M.", "clpid": "Burns-S-M" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/585wz-fra78", "publisher": "California Institute of Technology", "publication_date": "1988-01-01" }, { "id": "authors:3sb8a-cvh96", "collection": "authors", "collection_id": "3sb8a-cvh96", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1988.cs-tr-88-13", "type": "monograph", "title": "A Message-Passing Model for Highly Concurrent Computation", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/3sb8a-cvh96", "publisher": "California Institute of Technology", "publication_date": "1988-01-01" }, { "id": "authors:cgpwa-2j421", "collection": "authors", "collection_id": "cgpwa-2j421", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1987.5253-tr-87", "type": "monograph", "title": "Synthesis of Self-Timed Circuits by Program Transformation", "author": [ { "family_name": "Burns", "given_name": "Steven M.", "clpid": "Burns-S-M" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/cgpwa-2j421", "publisher": "California Institute of Technology", "publication_date": "1987-01-01" }, { "id": "authors:649ae-we761", "collection": "authors", "collection_id": "649ae-we761", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1987.5256-tr-87", "type": "monograph", "title": "A Synthesis Method for Self-Timed VLSI Circuits", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/649ae-we761", "publisher": "California Institute of Technology", "publication_date": "1987-01-01" }, { "id": "authors:7cknj-w1w80", "collection": "authors", "collection_id": "7cknj-w1w80", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1987.5240-tr-87", "type": "monograph", "title": "Submicron Systems Architecture: Semiannual Technical Report", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "McEliece", "given_name": "Robert J.", "clpid": "McEliece-R-J" }, { "family_name": "Rem", "given_name": "Martin", "clpid": "Rem-M" } ], "abstract": "No abstract available.", "doi": "10.7907/7cknj-w1w80", "publisher": "California Institute of Technology", "publication_date": "1987-01-01" }, { "id": "authors:2gjaq-xex23", "collection": "authors", "collection_id": "2gjaq-xex23", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1986.5212-tr-86", "type": "monograph", "title": "On Seitz' Arbiter", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No Abstract.", "doi": "10.7907/2gjaq-xex23", "publisher": "California Institute of Technology", "publication_date": "1986-01-01" }, { "id": "authors:brq3w-kj598", "collection": "authors", "collection_id": "brq3w-kj598", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1986.5221-tr-86", "type": "monograph", "title": "The Sync Model: A Parallel Execution Method for Logic Programming", "author": [ { "family_name": "Li", "given_name": "Peggy Pey-yun", "clpid": "Li-P-P-y" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "The Sync Model, a parallel execution method for logic programming, is proposed. The Sync Model is a multiple-solution data-driven model that realizes AND parallelism and OR-parallelism in a logic program assuming a message-passing multiprocessor system. AND parallelism is implemented by constructing a dynamic data flow graph of the literals in the clause body with an ordering algorithm. OR parallelism is achieved by adding special Synchronization signals to the stream partial solutions and synchronizing the multiple streams with a merge algorithr\nThe ordering algorithm and the merge algorithm are described. The merge algrithm is proved to be correct and therefore, the Sync Model is proved complete, i.e\nthe execution of a logic program under the Sync Model generates all the solution", "doi": "10.7907/brq3w-kj598", "publisher": "California Institute of Technology", "publication_date": "1986-01-01" }, { "id": "authors:jssn5-rbp39", "collection": "authors", "collection_id": "jssn5-rbp39", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1986.5211-tr-86", "type": "monograph", "title": "Self-Timed FIFO: An exercise in Compiling Programs into VLSI Circuits", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No Abstract.", "doi": "10.7907/jssn5-rbp39", "publisher": "California Institute of Technology", "publication_date": "1986-01-01" }, { "id": "authors:my65t-e9565", "collection": "authors", "collection_id": "my65t-e9565", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1986.5235-tr-86", "type": "monograph", "title": "Submicron Systems Architecture: Semiannual Technical Report", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Kajiya", "given_name": "James T.", "clpid": "Kajiya-J-T" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "McEliece", "given_name": "Robert J.", "clpid": "McEliece-R-J" }, { "family_name": "Rem", "given_name": "Martin", "clpid": "Rem-M" } ], "abstract": "No abstract available.", "doi": "10.7907/my65t-e9565", "publisher": "California Institute of Technology", "publication_date": "1986-01-01" }, { "id": "authors:pnf93-qxd46", "collection": "authors", "collection_id": "pnf93-qxd46", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1986.5210-tr-86", "type": "monograph", "title": "Compiling Communicating Processes into Delay-Insensitive VLSI Circuits", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract available.", "doi": "10.7907/pnf93-qxd46", "publisher": "California Institute of Technology", "publication_date": "1986-01-01" }, { "id": "authors:rzewj-csb10", "collection": "authors", "collection_id": "rzewj-csb10", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1986.5220-tr-86", "type": "monograph", "title": "Submicron Systems Architecture: Semiannual Technical Report", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Kajiya", "given_name": "James T.", "clpid": "Kajiya-J-T" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "McEliece", "given_name": "Robert J.", "clpid": "McEliece-R-J" }, { "family_name": "Rem", "given_name": "Martin", "clpid": "Rem-M" } ], "abstract": "No abstract available.", "doi": "10.7907/rzewj-csb10", "publisher": "California Institute of Technology", "publication_date": "1986-01-01" }, { "id": "authors:7fbb9-smt37", "collection": "authors", "collection_id": "7fbb9-smt37", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1985.5178-tr-85", "type": "monograph", "title": "Submicron Systems Architecture: Semiannual Technical Report", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Kajiya", "given_name": "James T.", "clpid": "Kajiya-J-T" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "McEliece", "given_name": "Robert J.", "clpid": "McEliece-R-J" }, { "family_name": "Rem", "given_name": "Martin", "clpid": "Rem-M" }, { "family_name": "Van Tilborg", "given_name": "Henk", "clpid": "Van-Tilborg-H-C-A" } ], "abstract": "No abstract available.", "doi": "10.7907/7fbb9-smt37", "publisher": "California Institute of Technology", "publication_date": "1985-03" }, { "id": "authors:0qedb-76g96", "collection": "authors", "collection_id": "0qedb-76g96", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1985.5195-tr-85", "type": "monograph", "title": "A New Generalization of Dekker's Algorithm for Mutual Exclusion", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No abstract.", "doi": "10.7907/0qedb-76g96", "publisher": "California Institute of Technology", "publication_date": "1985-01-01" }, { "id": "authors:cchf5-w1g63", "collection": "authors", "collection_id": "cchf5-w1g63", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1985.5193-tr-85", "type": "monograph", "title": "A Delay-insensitive Fair Arbiter", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No Abstract. Note: report is dated June 1985, May 1986", "doi": "10.7907/cchf5-w1g63", "publisher": "California Institute of Technology", "publication_date": "1985-01-01" }, { "id": "authors:mrh1j-cjp65", "collection": "authors", "collection_id": "mrh1j-cjp65", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1985.5202-tr-85", "type": "monograph", "title": "Submicron Systems Architecture: Semiannual Technical Report", "author": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" }, { "family_name": "Kajiya", "given_name": "James T.", "clpid": "Kajiya-J-T" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "McEliece", "given_name": "Robert J.", "clpid": "McEliece-R-J" }, { "family_name": "Rem", "given_name": "Martin", "clpid": "Rem-M" } ], "abstract": "No abstract available.", "doi": "10.7907/mrh1j-cjp65", "publisher": "California Institute of Technology", "publication_date": "1985-01-01" }, { "id": "authors:8nwds-15p23", "collection": "authors", "collection_id": "8nwds-15p23", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1984.5148-tr-84", "type": "monograph", "title": "Fair Mutual Exclusion with Unfair P and V Operations", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Burch", "given_name": "Jerry R.", "clpid": "Burch-J-R" } ], "abstract": "No Abstract.", "doi": "10.7907/8nwds-15p23", "publisher": "California Institute of Technology", "publication_date": "1984-01-01" }, { "id": "authors:w8azk-3fk36", "collection": "authors", "collection_id": "w8azk-3fk36", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1984.5124-tr-84", "type": "monograph", "title": "The Probe: An Addition to Communication Primitives", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No Abstract.", "doi": "10.7907/w8azk-3fk36", "publisher": "California Institute of Technology", "publication_date": "1984-01-01" }, { "id": "authors:abxcf-t3r94", "collection": "authors", "collection_id": "abxcf-t3r94", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1984.5147-tr-84", "type": "monograph", "title": "Networks of Machines for Distributed Recursive Computations", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Van de Snepscheut", "given_name": "Jan L. A.", "clpid": "Van-de-Snepscheut-J-L-A" } ], "abstract": "Distributed computations may be viewed as a set of communicating \nprocesses. If such a computation is to be executed by a multi-processor\nsystem, the processes have to be distributed over the processors and the\ncommunications have to be distributed over a network.\nThis leads to the questions of load balancing and message routing. In\nthis paper we consider distributed recursive computations and we propose a\nclass of processor networks that admits a homogeneous dist ribution of processes and trivial routing. Furthermore, we identify a subclass that\nadmits a planar embedding of the network.", "doi": "10.7907/abxcf-t3r94", "publisher": "California Institute of Technology", "publication_date": "1984-01-01" }, { "id": "authors:t0t4e-aq296", "collection": "authors", "collection_id": "t0t4e-aq296", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1984.5080-tr-83", "type": "monograph", "title": "Distributed Mutual Exclusion on a Ring of Processes", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "A set of processes called \"masters\" are sharing a critical section on a\nmutual exclusion basis. The servers communicate with each other in a ring. \nThree solutions for solving the mutual exclusion problem are presented. \nThey all rely on the\npresence of a unique privilege in the ring. The notation used extends CSP\ninput and output commands with a Boolean primitive, the \"probe\", which makes\nit possible to determine whether a communication action is pending on a\nchannel.\nA master communicates only with its private \"server\".\nIn the correctness proofs, the concept of \"trace\" is introduced, i.e. a\ntotal ordering of actions corresponding to a possible interleaving of the\natomic actions of a concurrent computation.\n[Note: report includes the date April 83/October 83 but published in 1984]", "doi": "10.7907/t0t4e-aq296", "publisher": "California Institute of Technology", "publication_date": "1984-01-01" }, { "id": "authors:b2dbm-s0762", "collection": "authors", "collection_id": "b2dbm-s0762", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1983.5097-tr-83", "type": "monograph", "title": "The Design of a Self-timed Circuit for Distributed Mutual Exclusion", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "No Abstract.", "doi": "10.7907/b2dbm-s0762", "publisher": "California Institute of Technology", "publication_date": "1983-01-01" }, { "id": "authors:desx8-jhv04", "collection": "authors", "collection_id": "desx8-jhv04", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1983.5075-tr-83", "type": "monograph", "title": "A General Proof Rule for Procedures in Predicate Transformer Semantics", "author": [ { "family_name": "Martin", "given_name": "Alain J", "clpid": "Martin-A-J" } ], "abstract": "Given a general definition of the procedure call based on the\nsubstitution rule for assignment, a general proof rule is derived for\nprocedures with unrestricted value, result, and value- result parameters,\nand global variables in the body of the procedure. It is then extended\nfor recursive procedures. Assuming that it has been proved that the body\nestablishes a certain postcondition I, the \"intention,\" for a certain\nprecondition J, the proof rule permitting to determine under which\nconditions a certain procedure call establishes the post condition E, the\n\"extension\", is based on finding an \"adaptation\" A , a s weak as possible,\nsuch that A ~ I -- E ( E ' is derived from E by some substitution of parameter variables.) It is preferable, but not essential, that the body\nbe \"transparent \" for the value parameters, i.e . , that the value parameters are not changed by the body.", "doi": "10.7907/desx8-jhv04", "publisher": "California Institute of Technology", "publication_date": "1983-01-01" }, { "id": "authors:cazcq-6fz54", "collection": "authors", "collection_id": "cazcq-6fz54", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1982.5047-tr-82", "type": "monograph", "title": "The torus: an exercise in constructing a processing surface", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "A \"Processing Surface\" is defined as a large, dense, and\nregular arrangement of processor and storage modules on a two-dimensional surface, e.g. a VLSI chip. A general method is described for distributing parallel recursive computations over such a surface. Scope rules enforcing\nthe \"locality\" of variables and procedure parameters are introduced in the programming language. These rules and a particular interconnection of the modules on the surface make it possible to transmit parameter and variable\nvalues between modules without using extraneous communication actions.\n\nThe choice of the Processing Surface topology for binary recursive computations is discussed and a torus-like topology is chosen.", "doi": "10.7907/cazcq-6fz54", "publisher": "California Institute of Technology", "publication_date": "1982" }, { "id": "authors:c1h76-gdn90", "collection": "authors", "collection_id": "c1h76-gdn90", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20120418-114041991", "type": "monograph", "title": "A Distributed Implementation Method for Parallel Programming", "author": [ { "family_name": "Martin", "given_name": "A. J.", "clpid": "Martin-A-J" } ], "abstract": "A method is described for implementing on a finite network of processing \"cells\", called the \"implementation graph\", programs whose potential parallelism is not fixed by the implementation but varies according to the input parameters. First, programming constructs are described\npermitting a computation, regarded as a dynamic structure called the \"computation graph\", to diffuse through the implementation graph. Second, the implementation problem of\nmapping an unbounded number of computation nodes on a finite number of cells is tackled. Processor allocation and message buffering completely disappear from the programmer's concerns. The mechanism proposed is considered a generalization of the stack mechanism.", "doi": "10.7907/c1h76-gdn90", "publisher": "California Institute of Technology", "publication_date": "1980" } ]