<h1>Martin, Alain</h1>
<h2>Monograph from <a href="https://data.caltech.edu">CaltechTHESIS committee</a></h2>
<ul>
<li>Keller, Sean Jason (2014) <a href="https://resolver.caltech.edu/CaltechTHESIS:08172013-192316055">Robust Near-Threshold QDI Circuit Analysis and Design</a>; <a href="https://doi.org/10.7907/79EJ-Q945">10.7907/79EJ-Q945</a></li>
<li>Mehta, Nikil (2013) <a href="https://resolver.caltech.edu/CaltechTHESIS:10072012-230900231">An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping</a>; <a href="https://doi.org/10.7907/358S-CW22">10.7907/358S-CW22</a></li>
<li>DeLorimier, Michael John (2013) <a href="https://resolver.caltech.edu/CaltechTHESIS:08192012-145253489">GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms</a>; <a href="https://doi.org/10.7907/M3TW-7Y53">10.7907/M3TW-7Y53</a></li>
<li>White, Jerome S. (2011) <a href="https://resolver.caltech.edu/CaltechTHESIS:05312011-123940546">Applying Formal Methods to Distributed Algorithms Using Local-Global Relations  </a>; <a href="https://doi.org/10.7907/8FRW-ZF17">10.7907/8FRW-ZF17</a></li>
<li>Kapre, Nachiket Ganesh (2011) <a href="https://resolver.caltech.edu/CaltechTHESIS:10262010-082537998">SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator
</a>; <a href="https://doi.org/10.7907/QVZR-VB52">10.7907/QVZR-VB52</a></li>
<li>Naeimi, Helia (2008) <a href="https://resolver.caltech.edu/CaltechETD:etd-01242008-012650">Reliable Integration of Terascale Systems with Nanoscale Devices</a>; <a href="https://doi.org/10.7907/P842-7B49">10.7907/P842-7B49</a></li>
<li>Prakash, Piyush (2008) <a href="https://resolver.caltech.edu/CaltechETD:etd-05262008-234258">Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching</a>; <a href="https://doi.org/10.7907/9HMY-RR92">10.7907/9HMY-RR92</a></li>
<li>Pratap, Amrit (2008) <a href="https://resolver.caltech.edu/CaltechETD:etd-05292008-231048">Adaptive Learning Algorithms and Data Cloning</a>; <a href="https://doi.org/10.7907/GV3D-AB69">10.7907/GV3D-AB69</a></li>
<li>Jang, Wonjin (2008) <a href="https://resolver.caltech.edu/CaltechETD:etd-11092007-180524">Soft-Error Tolerant Quasi Delay-insensitive Circuits</a>; <a href="https://doi.org/10.7907/ZVFF-WE07">10.7907/ZVFF-WE07</a></li>
<li>Basset, Christophe Jean-Michel (2007) <a href="https://resolver.caltech.edu/CaltechETD:etd-04262007-131214">CMOS Imaging Technology with Embedded Early Image Processing</a>; <a href="https://doi.org/10.7907/2GZN-T836">10.7907/2GZN-T836</a></li>
<li>Yu, Xin (2007) <a href="https://resolver.caltech.edu/CaltechETD:etd-05222007-211909">Reflection and Its Application to Mechanized MetaReasoning About Programming Languages</a>; <a href="https://doi.org/10.7907/S0HG-RT72">10.7907/S0HG-RT72</a></li>
<li>Papadantonakis, Karl Spyros (2006) <a href="https://resolver.caltech.edu/CaltechETD:etd-01132006-152609">Rigorous Analog Verification of Asynchronous Circuits</a>; <a href="https://doi.org/10.7907/4R8F-WF03">10.7907/4R8F-WF03</a></li>
<li>Riedel, Marcus D. (2004) <a href="https://resolver.caltech.edu/CaltechETD:etd-05032004-153842">Cyclic Combinational Circuits</a>; <a href="https://doi.org/10.7907/410B-XR25">10.7907/410B-XR25</a></li>
<li>Wong, Catherine Grace (2004) <a href="https://resolver.caltech.edu/CaltechTHESIS:11192009-161338958">High-Level Synthesis and Rapid Prototyping of Asynchronous VLSI Systems</a>; <a href="https://doi.org/10.7907/5N2N-0W58">10.7907/5N2N-0W58</a></li>
<li>Pénzes, Paul Ivan (2002) <a href="https://resolver.caltech.edu/CaltechTHESIS:03022011-131111881">Energy-Delay Complexity of Asynchronous Circuits</a>; <a href="https://doi.org/10.7907/9jpj-5s67">10.7907/9jpj-5s67</a></li>
<li>Zimmerman, Daniel Marc (2002) <a href="https://resolver.caltech.edu/CaltechETD:etd-12072001-160019">Dynamic UNITY</a>; <a href="https://doi.org/10.7907/AC6E-WE21">10.7907/AC6E-WE21</a></li>
<li>Koosh, Vincent Frank (2001) <a href="https://resolver.caltech.edu/CaltechETD:etd-10022001-201911">Analog Computation and Learning in VLSI</a>; <a href="https://doi.org/10.7907/9B65-TB43">10.7907/9B65-TB43</a></li>
<li>Schooler, Eve Meryl (2001) <a href="https://resolver.caltech.edu/CaltechETD:etd-08272001-155016">Why multicast protocols (don't) scale: an analysis of multipoint algorithms for scalable group communication</a>; <a href="https://doi.org/10.7907/44QZ-R465">10.7907/44QZ-R465</a></li>
<li>Nyström, Mika (2001) <a href="https://resolver.caltech.edu/CaltechTHESIS:10152010-145548970">Asynchronous Pulse Logic</a>; <a href="https://doi.org/10.7907/B107-MW15">10.7907/B107-MW15</a></li>
<li>Manohar, Rajit (1999) <a href="https://resolver.caltech.edu/CaltechETD:etd-08112005-114144">The impact of asynchrony on computer architecture</a>; <a href="https://doi.org/10.7907/xzwa-p598">10.7907/xzwa-p598</a></li>
<li>Massingill, Berna Linda (1998) <a href="https://resolver.caltech.edu/CaltechETD:etd-01242008-074143">A structured approach to parallel programming</a>; <a href="https://doi.org/10.7907/5ma9-h225">10.7907/5ma9-h225</a></li>
<li>Sivilotti, Paolo A. G. (1998) <a href="https://resolver.caltech.edu/CaltechETD:etd-01252008-095244">A method for the specification, composition, and testing of distributed object systems</a>; <a href="https://doi.org/10.7907/z89g-gm27">10.7907/z89g-gm27</a></li>
<li>Boahen, Kwabena Adu (1997) <a href="https://resolver.caltech.edu/CaltechETD:etd-01092008-085128">Retinomorphic vision systems : reverse engineering the vertebrate retina</a>; <a href="https://doi.org/10.7907/96W6-N605">10.7907/96W6-N605</a></li>
<li>Van der Goot, Marcel Rene (1995) <a href="https://resolver.caltech.edu/CaltechETD:etd-10162007-093427">Semantics of VLSI synthesis</a>; <a href="https://doi.org/10.7907/SR5V-KT18">10.7907/SR5V-KT18</a></li>
<li>Leino, K. Rustan M. (1995) <a href="https://resolver.caltech.edu/CaltechETD:etd-10162007-111256">Toward reliable modular programs</a>; <a href="https://doi.org/10.7907/ynt2-nn65">10.7907/ynt2-nn65</a></li>
<li>Lee, Tak Kwan (1995) <a href="https://resolver.caltech.edu/CaltechETD:etd-10172007-090528">A General Approach to Performance Analysis and Optimization of Asynchronous Circuits</a>; <a href="https://doi.org/10.7907/ehzs-y537">10.7907/ehzs-y537</a></li>
<li>Hofstee, H. Peter (1995) <a href="https://resolver.caltech.edu/CaltechETD:etd-10112007-083903">Synchronizing processes</a>; <a href="https://doi.org/10.7907/G620-GG65">10.7907/G620-GG65</a></li>
<li>Ko, Tsz-Mei (1993) <a href="https://resolver.caltech.edu/CaltechETD:etd-08302007-094049">On the VLSI decompositions for complete graphs, DeBruijn graphs, hypercubes, hyperplanes, meshes, and shuffle-exchange graphs</a>; <a href="https://doi.org/10.7907/s7w7-a995">10.7907/s7w7-a995</a></li>
<li>Hazewindus, Pieter Johannes (1992) <a href="https://resolver.caltech.edu/CaltechETD:etd-07202007-132706">Testing delay-insensitive circuits</a>; <a href="https://doi.org/10.7907/0d7v-9d09">10.7907/0d7v-9d09</a></li>
<li>Mahowald, Michelle A. (Misha) (1992) <a href="https://resolver.caltech.edu/CaltechTHESIS:09122011-094355148">VLSI Analogs of Neuronal Visual Processing: A Synthesis of Form and Function</a>; <a href="https://doi.org/10.7907/4bdw-fg34">10.7907/4bdw-fg34</a></li>
<li>Burns, Steven Morgan (1991) <a href="https://resolver.caltech.edu/CaltechETD:etd-07092007-072640">Performance analysis and optimization of asynchronous circuits</a>; <a href="https://doi.org/10.7907/kez1-7q52">10.7907/kez1-7q52</a></li>
<li>Sivilotti, Massimo Antonio (1991) <a href="https://resolver.caltech.edu/CaltechETD:etd-07122007-134330">Wiring Considerations in Analog VLSI Systems, with Application to Field-Programmable Networks</a>; <a href="https://doi.org/10.7907/stj4-kh72">10.7907/stj4-kh72</a></li>
<li>Su, Wen-King (1990) <a href="https://resolver.caltech.edu/CaltechTHESIS:03222012-091423469">Reactive-Process Programming and Distributed Discrete-Event Simulation</a>; <a href="https://doi.org/10.7907/9qzd-kv20">10.7907/9qzd-kv20</a></li>
<li>Ngai, John Yee-Keung (1989) <a href="https://resolver.caltech.edu/CaltechETD:etd-02132007-153533">A Framework for Adaptive Routing in Multicomputer Networks</a>; <a href="https://doi.org/10.7907/a01h-0z81">10.7907/a01h-0z81</a></li>
<li>Choo, Young-il (1987) <a href="https://resolver.caltech.edu/CaltechETD:etd-02282008-111427">Logic from Programming Language Semantics</a>; <a href="https://doi.org/10.7907/r9hf-1b88">10.7907/r9hf-1b88</a></li>
<li>Athas, William C., Jr. (1987) <a href="https://resolver.caltech.edu/CaltechETD:etd-02282008-091326">Fine Grain Concurrent Computations</a>; <a href="https://doi.org/10.7907/63xc-r308">10.7907/63xc-r308</a></li>
<li>Dally, William James (1986) <a href="https://resolver.caltech.edu/CaltechETD:etd-03252008-140428">A VLSI Architecture for Concurrent Data Structures</a>; <a href="https://doi.org/10.7907/f8d5-x741">10.7907/f8d5-x741</a></li>
<li>Li, Peyyun Peggy (1986) <a href="https://resolver.caltech.edu/CaltechETD:etd-03192008-143903">A Parallel Execution Model for Logic Programming</a>; <a href="https://doi.org/10.7907/2ngs-bp80">10.7907/2ngs-bp80</a></li>
<li>El-Hamamsy, Sayed-Amr (1986) <a href="https://resolver.caltech.edu/CaltechETD:etd-03262008-092115">Coupled-Inductor Inversion, Rectification and Cycloconversion</a>; <a href="https://doi.org/10.7907/BHKX-4J16">10.7907/BHKX-4J16</a></li>
<li>Lien, Sheue-Ling Chang (1985) <a href="https://resolver.caltech.edu/CaltechETD:etd-04102008-142130">Combining Computation with Geometry</a>; <a href="https://doi.org/10.7907/n1qe-h846">10.7907/n1qe-h846</a></li>
<li>Chen, Marina Chien-mei (1983) <a href="https://resolver.caltech.edu/CaltechETD:etd-08312006-094203">Space-time Algorithms: Semantics and Methodology</a>; <a href="https://doi.org/10.7907/bfpj-t811">10.7907/bfpj-t811</a></li>
<li>Lang, Charles Richard, Jr. (1982) <a href="https://resolver.caltech.edu/CaltechETD:etd-09142006-085516">The Extension of Object-Oriented Languages to a Homogeneous, Concurrent Architecture</a>; <a href="https://doi.org/10.7907/9EVC-2X08">10.7907/9EVC-2X08</a></li>
</ul>