[ { "id": "authors:m9w4x-8r742", "collection": "authors", "collection_id": "m9w4x-8r742", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20141106-133106801", "type": "article", "title": "A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold", "author": [ { "family_name": "Keller", "given_name": "Sean", "clpid": "Keller-S" }, { "family_name": "Harris", "given_name": "David Money", "clpid": "Harris-D-M" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "Power dissipation is currently one of the most important design constraints in digital systems. In order to reduce power and energy demands in the foremost technology, namely CMOS, it is necessary to reduce the supply voltage to near the device threshold voltage. Existing analytical models for MOS devices are either too complex, thus obscuring the basic physical relations between voltages and currents, or they are inaccurate and discontinuous around the region of interest, i.e., near threshold. This paper presents a simple transregional compact model for analyzing digital circuits around the threshold voltage. The model is continuous, physically derived (by way of a simplified inversion-charge approximation), and accurate over a wide operational range: from a few times the thermal voltage to approximately twice the threshold voltage in modern technologies.", "doi": "10.1109/TVLSI.2013.2282316", "issn": "1063-8210", "publisher": "IEEE", "publication": "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", "publication_date": "2014-10", "series_number": "10", "volume": "22", "issue": "10", "pages": "2041-2053" }, { "id": "authors:x2ttg-dxf63", "collection": "authors", "collection_id": "x2ttg-dxf63", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:MARprocieee06", "type": "article", "title": "Asynchronous techniques for system-on-chip design", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Nystr\u00f6m", "given_name": "Mika", "clpid": "Nystr\u00f6m-M" } ], "abstract": "SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.", "doi": "10.1109/JPROC.2006.875789", "issn": "0018-9219", "publisher": "Proceedings of the IEEE", "publication": "Proceedings of the IEEE", "publication_date": "2006-06", "series_number": "6", "volume": "94", "issue": "6", "pages": "1089-1120" }, { "id": "authors:rsjyk-jb663", "collection": "authors", "collection_id": "rsjyk-jb663", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20170409-083932724", "type": "article", "title": "Specifying the Caltech asynchronous microprocessor", "author": [ { "family_name": "Back", "given_name": "R. J. R.", "clpid": "Back-R-J-R" }, { "family_name": "Martin", "given_name": "A. J.", "clpid": "Martin-A-J" }, { "family_name": "Sere", "given_name": "K.", "clpid": "Sere-K" } ], "abstract": "The action systems framework for modelling parallel programs is used to formally specify a microprocessor. First the microprocessor is specified as a sequential program. The sequential specification is then decomposed and refined into a concurrent program using correctness-preserving program transformations. Previously this microprocessor has been specified at Caltech, where an asynchronous circuit for the microprocessor was derived from the specification. We propose a specification strategy that is based on the idea of spatial decomposition of the program variable space.", "doi": "10.1016/0167-6423(95)00023-2", "issn": "0167-6423", "publisher": "Elsevier", "publication": "Science of Computer Programming", "publication_date": "1996-05", "series_number": "1-3", "volume": "26", "issue": "1-3", "pages": "79-97" }, { "id": "authors:qpaar-1eb62", "collection": "authors", "collection_id": "qpaar-1eb62", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:TIEieeedtc94", "type": "article", "title": "A 100-MIPS GaAs asynchronous microprocessor", "author": [ { "family_name": "Tierno", "given_name": "Jos\u00e9 A.", "clpid": "Tierno-J-A" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Borkovic", "given_name": "Drazen", "clpid": "Borkovic-D" }, { "family_name": "Lee", "given_name": "Tak Kwan", "clpid": "Lee-Tak-Kwan" } ], "abstract": "The authors describe how they ported an asynchronous microprocessor previously implemented in CMOS to gallium arsenide, using a technology-independent asynchronous design technique. They introduce new circuits including a sense-amplifier, a completion detection circuit, and a general circuit structure for operators specified by production rules. The authors used and tested these circuits in a variety of designs.", "doi": "10.1109/54.282444", "issn": "1084-7529", "publisher": "IEEE", "publication": "IEEE Design and Test of Computers", "publication_date": "1994", "series_number": "2", "volume": "11", "issue": "2", "pages": "43-49" }, { "id": "authors:vbcxz-mtz48", "collection": "authors", "collection_id": "vbcxz-mtz48", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20170830-083320673", "type": "article", "title": "Distributed sorting", "author": [ { "family_name": "Hofstee", "given_name": "H. Peter", "clpid": "Hofstee-H-P" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Van de Snepscheut", "given_name": "Jan L. A.", "clpid": "Van-de-Snepscheut-J-L-A" } ], "abstract": "In this paper we present a distributed sorting algorithm, which is a variation on exchange sort, i.e., neighboring elements that are out of order are exchanged. We derive the algorithm by transforming a sequential algorithm into a distributed one. The transformation is guided by the distribution of the data over processes. First we discuss the case of two processes, and then the general case of one or more processes. Finally we propose a more efficient solution for the general case.", "doi": "10.1016/0167-6423(90)90081-N", "issn": "0167-6423", "publisher": "Elsevier", "publication": "Science of Computer Programming", "publication_date": "1990-12", "series_number": "2-3", "volume": "15", "issue": "2-3", "pages": "119-133" }, { "id": "authors:grxpn-mmm53", "collection": "authors", "collection_id": "grxpn-mmm53", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20161130-144153368", "type": "article", "title": "The design of an asynchronous microprocessor", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Burns", "given_name": "Steven M.", "clpid": "Burns-S-M" }, { "family_name": "Lee", "given_name": "T. K.", "clpid": "Lee-T-K" }, { "family_name": "Borkovic", "given_name": "Drazen", "clpid": "Borkovic-D" }, { "family_name": "Hazewindus", "given_name": "Pieter J.", "clpid": "Hazewindus-P-J" } ], "abstract": "[no abstract]", "issn": "0163-5964", "publisher": "ACM", "publication": "ACM SIGARCH Computer Architecture News", "publication_date": "1989-06", "series_number": "4", "volume": "17", "issue": "4", "pages": "99-110" }, { "id": "authors:44vxf-0w021", "collection": "authors", "collection_id": "44vxf-0w021", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20161130-145428229", "type": "article", "title": "The first asynchronous microprocessor: the test results", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Burns", "given_name": "Steven M.", "clpid": "Burns-S-M" }, { "family_name": "Lee", "given_name": "T. K.", "clpid": "Lee-T-K" }, { "family_name": "Borkovic", "given_name": "Drazen", "clpid": "Borkovic-D" }, { "family_name": "Hazewindus", "given_name": "Pieter J.", "clpid": "Hazewindus-P-J" } ], "abstract": "We have designed the first entirely asynchronous (also called self-timed or delay-insensitive)\nmicroprocessor. The design was reported at the Decennial Caltech Conference on VLSI, last March. The conference paper is included here as an appendix. Since the chips had not yet been fabricated at the moment of writing\nthe conference paper, the paper does not include the results of the experiment. The purpose of this note is to publish these results, which are quite remarkable\nbecause of the speed reached on this first design, and, as importantly, because of the surprising robustness of the chips to variations in temperature and VDD voltage\nvalues.", "doi": "10.1145/71317.71324", "issn": "0163-5964", "publisher": "ACM", "publication": "ACM SIGARCH Computer Architecture News", "publication_date": "1989-06", "series_number": "4", "volume": "17", "issue": "4", "pages": "95-98" }, { "id": "authors:ghkt8-r2w95", "collection": "authors", "collection_id": "ghkt8-r2w95", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20161130-142130832", "type": "article", "title": "On David Gries's plateau problem", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "[no abstract]", "doi": "10.1145/1005968.1005974", "issn": "0163-5948", "publisher": "ACM", "publication": "ACM SIGSOFT Software Engineering Notes", "publication_date": "1984-01", "series_number": "1", "volume": "9", "issue": "1", "pages": "29-30" }, { "id": "authors:8q5hm-qnk74", "collection": "authors", "collection_id": "8q5hm-qnk74", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190111-145202534", "type": "article", "title": "A Characterization of Product-Form Queuing Networks", "author": [ { "family_name": "Chandy", "given_name": "K. M.", "clpid": "Chandy-K-M" }, { "family_name": "Martin", "given_name": "A. J.", "clpid": "Martin-A-J" } ], "abstract": "Queuing network models have proved effective in the design and analysis of computing systems. The class of queuing network models having product-form solutions is amenable to efficient, general solution techniques. The purpose of this\npaper is to characterize such queuing systems. With this characterization it will be easy to determine whether the product-form algorithms can be used to analyze a system.", "doi": "10.1145/322374.322378", "issn": "0004-5411", "publisher": "Association for Computing Machinery", "publication": "Journal of the ACM", "publication_date": "1983-04", "series_number": "2", "volume": "30", "issue": "2", "pages": "286-299" }, { "id": "authors:qsz11-hyb18", "collection": "authors", "collection_id": "qsz11-hyb18", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1982.5046-tr-82", "type": "article", "title": "An Axiomatic Definition of Synchronization Primitives", "author": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" } ], "abstract": "The semantics of a pair of synchronization primitives is characterized by three fundamental axioms: boundedness, progress, and fairness. The class of primitives fulfilling the three axioms is semantically defined. Unbuffered communication primitives, the symmetrical P and V operations, and the usual P and V operations are proved to be the three instances of this class. The definitions obtained are used to prove a series of basic\ntheorems on mutual exclusion, producer-consumer coupling, deadlock, and linear and circular arrangements of communicating buffer-processes. An implementation of P and V operations fulfilling the axioms is proposed.", "doi": "10.1007/BF00261260", "issn": "0001-5903", "publisher": "Springer-Verlag", "publication": "Acta Informatica", "publication_date": "1981-10", "series_number": "2", "volume": "16", "issue": "2", "pages": "219-235" } ]