A homogeneous machine architecture, consisting of a regular interconnection of many identical elements, exploits the economic benefits of VLSI technology. A concurrent programming model is presented that is related to object oriented languages such as Simula and Smalltalk. Techniques are developed which permit the execution of general purpose object oriented programs on a homogeneous machine. Both the hardware architecture and the supporting software algorithms are demonstrated to scale their performance with the size of the system.
\r\n\r\nThe program objects communicate by passing messages. Objects may move about in the system and may have an arbitrary pointer topology. A distributed, on-the-fly garbage collection algorithm is presented which operates by message passing. Simulation of the algorithm demonstrates its ability to collect obsolete objects over the entire machine with acceptable overhead costs. Algorithms for maintaining the locality of object references and for implementing a virtual object capability are also presented.
\r\n\r\nTo insure the absence of hardware bottlenecks, a number of interconnection strategies are discussed and simulated for use in a homogeneous machine. Of those considered, the Boolean N-cube connection is demonstrated to provide the necessary characteristics.
\r\n\r\nThe object oriented machine will provide increased performance as its size is increased. It can execute a general purpose, concurrent, object oriented language where the size of the machine and its interconnection topology are transparent to the programmer.
", "doi": "10.7907/9EVC-2X08", "publication_date": "1982", "thesis_type": "phd", "thesis_year": "1982" }, { "id": "thesis:10767", "collection": "thesis", "collection_id": "10767", "cite_using_url": "https://resolver.caltech.edu/CaltechThesis:03092018-151643742", "primary_object_url": { "basename": "2891_TR_79.pdf", "content": "final", "filesize": 19947993, "license": "other", "mime_type": "application/pdf", "url": "/10767/1/2891_TR_79.pdf", "version": "v3.0.0" }, "type": "thesis", "title": "Automated Wiring Analysis of Integrated Circuit Geometric Data", "author": [ { "family_name": "Lang", "given_name": "Charles Richard", "clpid": "Lang-Charles-Richard" } ], "thesis_advisor": [ { "family_name": "Seitz", "given_name": "Charles L.", "clpid": "Seitz-C-L" } ], "thesis_committee": [ { "family_name": "None", "given_name": "None" } ], "local_group": [ { "literal": "Computer Science Technical Reports" }, { "literal": "div_eng" } ], "abstract": "Methods are presented by which wiring data of an NMOS integrated circuit may be extracted from its mask information. The procedures involved utilize the capabilities of a general purpose polygon package. The polygon operations are defined to enhance their use in this application, however the package is suitable for other uses such as, design rule checking. The analysis is performed on hierarchical symbol definitions of mask geometry. The geometry is presumed to be described in CIF 2.0 (Caltech Intermediate Form). The analysis attempts to recognize three basic types of structures in the geometry:
\r\n\r\n1)\tTransistor devices (and capacitors)
\r\n2)\tLocal interconnection structures and
\r\n3)\tGlobal interconnection structures
Definitions are put forth for the distinction of global and local wires. The data extracted from the symbol geometry is the percent utilization of each symbol's area by each of the three types of structures. The purpose behind the extraction of this data is its use in the development and evaluation of wiring models for custom NMOS IC design. Two approaches are presented which extract such data. The first is heuristic and depends on built-in assumptions of how the NMOS process is generally used. This technique loses accuracy if a design style falls outside of these assumptions. The second technique is a method by which the topology of design may be extracted from the geometry. The geometric objects, from which devices and interconnections are made, are preserved, such that the wiring information can be obtained precisely. This method is complex and requires considerable computation, however, the topology extracted may also be used to verify the geometric data against the original design topology.
", "doi": "10.7907/qxbg-2c10", "publication_date": "1980", "thesis_type": "masters", "thesis_year": "1980" } ]