[ { "id": "authors:5kyg6-q3m53", "collection": "authors", "collection_id": "5kyg6-q3m53", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1982.4724-tr-82", "type": "monograph", "title": "Concurrent, Asynchronous Garbage Collection Among Cooperating Processors", "author": [ { "family_name": "Lang", "given_name": "Charles R.", "clpid": "Lang-Charles-Richard" } ], "abstract": "No Abstract.", "doi": "10.7907/5kyg6-q3m53", "publisher": "California Institute of Technology", "publication_date": "1982-01-01" }, { "id": "authors:e6pe5-r8y26", "collection": "authors", "collection_id": "e6pe5-r8y26", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1982.5014-tr-82", "type": "monograph", "title": "The Extension of Object-Oriented Languages to a Homogenous, Concurrent Architecture", "author": [ { "family_name": "Lang", "given_name": "Charles Richard", "clpid": "Lang-Charles-Richard" } ], "abstract": "A homogeneous machine architecture, consisting of a regular\ninterconnection of many identical elements, exploits the economic benefits of VLSI technology, A concurrent programming model is presented that is related to object oriented languages such as Simula and Smalltalk.\nTechniques are developed which permit the execution of general purpose object oriented programs on a homogeneous machine. Both the hardware architecture and the supporting software algorithms are demonstrated to scale their performance with the size of the system.\nThe program objects communicate by passing messages. Objects may move about in the system and may have an arbitrary pointer topology, A\ndistributed, on-the-fly garbage collection algorithm is presented which\noperates by message passing. Simulation of the algorithm demonstrates its\nability to collect obsolete objects over the entire machine with acceptable\noverhead costs. Algorithms for maintaining the locality of object references\nand for implementing a virtual object capability are also presented.\nTo insure the absence of hardware bottlenecks, a number of\ninterconnection strategies are discussed and simulated for use in a\nhomogeneous machine. Of those considered, the Boolean N-cube connection\nis demonstrated to provide the necessary characteristics.\nThe object oriented machine will provide increased performance as its\nsize is increased. It can execute a general purpose, concurrent, object\noriented language where the size of the machine and its interconnection\ntopology are transparent to the programmer.", "doi": "10.7907/e6pe5-r8y26", "publisher": "California Institute of Technology", "publication_date": "1982-01-01" }, { "id": "authors:n015c-49w50", "collection": "authors", "collection_id": "n015c-49w50", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1981.4336-tr-81", "type": "monograph", "title": "A Structured Design Methodology & Assoicated Software Tools", "author": [ { "family_name": "Trimberger", "given_name": "Stephen", "clpid": "Trimberger-S" }, { "family_name": "Rowson", "given_name": "James A.", "clpid": "Rowson-J-A" }, { "family_name": "Lang", "given_name": "Charles R.", "clpid": "Lang-Charles-Richard" }, { "family_name": "Gray", "given_name": "James P.", "clpid": "Gray-J-P" } ], "abstract": "The problems encountered designing very large scale integrated circuits (VLSI) are fundamentally different from the problems encountered in the design of small scale integrated circuits. The differences require a new methodology of design for the new large scale circuits, and the new design methodology requires a new set of tools. The computer aided design work at Caltech has progressed from a recognition of the inherent differences and has produced a new design methodology and a set of tools which attack the new problems in integrated circuit design.", "doi": "10.7907/n015c-49w50", "publisher": "California Institute of Technology", "publication_date": "1981-01-01" }, { "id": "authors:sn86y-q7468", "collection": "authors", "collection_id": "sn86y-q7468", "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1979.2891-tr-79", "type": "monograph", "title": "Automated Wiring Analysis of Integrated Circuit Geometric Data", "author": [ { "family_name": "Lang", "given_name": "Charles R.", "clpid": "Lang-Charles-Richard" } ], "abstract": "Methods are presented by which wiring data of an NMOS integrated circuit may be extracted from its mask information. The procedures involved utilize the capabilities of a general purpose polygon package. The polygon operations are defined to enhance their use in this application, however the package is suitable for other uses such as, design rule checking. The analysis is performed on hierarchical symbol definitions of mask geometry. The geometry is presumed to be described in CIF 2.0 (Caltech Intermediate Form). The analysis attempts to recognize three basic types of structures in the geometry: \n\n1)\tTransistor devices (and capacitors)\n2)\tLocal interconnection structures and \n3)\tGlobal interconnection structures\n\nDefinitions are put forth for the distinction of global and local wires. The data extracted from the symbol geometry is the percent utilization of each symbol's area by each of the three types of structures. The purpose behind the extraction of this data is its use in the development and evaluation of wiring models for custom NMOS IC design. Two approaches are presented which extract such data. The first is heuristic and depends on built-in assumptions of how the NMOS process is generally used. This technique loses accuracy if a design style falls outside of these assumptions. The second technique is a method by which the topology of design may be extracted from the geometry. The geometric objects, from which devices and interconnections are made, are preserved, such that the wiring information can be obtained precisely. This method is complex and requires considerable computation, however, the topology extracted may also be used to verify the geometric data against the original design topology.", "doi": "10.7907/sn86y-q7468", "publisher": "California Institute of Technology", "publication_date": "1979-08-09" } ]