@inbook{https://resolver.caltech.edu/CaltechAUTHORS:20190429-151824627,
    title = "ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems",
    chapter = "VLSI neural network with digital weights and analog multipliers",
    url = "https://resolver.caltech.edu/CaltechAUTHORS:20190429-151824627",
    id = "record",
    isbn = "0780366859",
    doi = "10.1109/iscas.2001.921290"
}


@inbook{https://resolver.caltech.edu/CaltechAUTHORS:20190405-154249828,
    title = "2001 IEEE International Symposium on Circuits and Systems",
    chapter = "Dynamic charge restoration of floating gate subthreshold MOS translinear circuits",
    url = "https://resolver.caltech.edu/CaltechAUTHORS:20190405-154249828",
    id = "record",
    isbn = "0-7803-6685-9",
    doi = "10.1109/ISCAS.2001.921781"
}


@inbook{https://resolver.caltech.edu/CaltechAUTHORS:20190326-112619359,
    title = "Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001",
    chapter = "Dynamic charge restoration of floating gate subthreshold MOS translinear circuits",
    url = "https://resolver.caltech.edu/CaltechAUTHORS:20190326-112619359",
    id = "record",
    isbn = "0-7695-1038-8",
    doi = "10.1109/ARVLSI.2001.915558"
}