[
    {
        "id": "authors:vvm2m-zpr34",
        "collection": "authors",
        "collection_id": "vvm2m-zpr34",
        "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1981.4530-tr-81",
        "type": "monograph",
        "title": "Silicon Compilation",
        "author": [
            {
                "family_name": "Johannsen",
                "given_name": "David Lawrence",
                "clpid": "Johannsen-David-Lawrence"
            }
        ],
        "abstract": "Modern integrated circuits are among the most complex systems designed by man.\nAlthough we have seen a rapid increase in fabrication technology, traditional\ndesign methodologies have not evolved at a rate commensurate with the increasing\ndesign complexity potential. These circuit design methodologies fail when applied\nto Very Large Scale Integrated (VLSI) circuit design. This thesis proposes a new\ndesign methodology which manages the complexity VLSI design, allowing\neconomical generation of correctly functioning circuits.\nCost is one measurement of a design methodology's value. A good design\nmethodology rapidly and efficiently translates high level system specifications into\nworking parts. Traditional techniques partition the translation process into many\nsteps: each design tool is focused upon one of these design steps. This partitioning\nprecludes the consideration of global constraints, and introduces a literal explosion\nof data being transfered between design steps. The design process becomes\nerror-prone and time consuming.\nThe technique of silicon compilation presented in this thesis automatically\ntranslates from high level specifications into correct geometric descriptions. In this\napproach, the designer interacts at a high level of abstraction, and need not be\nconcerned with lower levels of detail, facilitating exploration of alternate system\narchitectures. Furthermore, since the implementation is algorithmically generated,\nchip descriptions can be made correct by construction. Finally, the user is given\ntechnology independence, because the high level specification need not require\nknowledge of fabrication details. This flexibility allows the user to take advantage\nof technology advances.\nThis thesis explores various aspects of silicon compilation, and presents a prototype\ncompiler, Bristle Blocks. The methodology is demonstrated through the design of\nseveral chips. The practicality of the methodology results from the concern for\nefficiency of the design process and of the chip designs produced by the system.",
        "doi": "10.7907/vvm2m-zpr34",
        "publisher": "California Institute of Technology",
        "publication_date": "1981-05-13"
    },
    {
        "id": "authors:15bcb-29638",
        "collection": "authors",
        "collection_id": "15bcb-29638",
        "cite_using_url": "https://resolver.caltech.edu/CaltechCSTR:1978.2069-tr-78",
        "type": "monograph",
        "title": "Hierarchical power routing",
        "author": [
            {
                "family_name": "Johannsen",
                "given_name": "Dave",
                "clpid": "Johannsen-David-Lawrence"
            }
        ],
        "abstract": "Advances in LSI technology allow the system designer to implement large amounts of processing capability on a single silicon chip. It will soon be possible to construct a large number of processing elements on these chips. How will the system designer organize these processing elements? Hierarchically designed array or tree machines arc two possible alternatives. This paper provides a background for study of array and tree machines by examining how to supply power to an array of processing elements.",
        "doi": "10.7907/15bcb-29638",
        "publisher": "California Institute of Technology",
        "publication_date": "1978-10-17"
    }
]