[ { "id": "authors:7qj9a-jtw26", "collection": "authors", "collection_id": "7qj9a-jtw26", "cite_using_url": "https://authors.library.caltech.edu/records/7qj9a-jtw26", "type": "article", "title": "A 192-Channel 1D CNN-Based Neural Feature Extractor in 65nm CMOS for Brain-Machine Interfaces", "author": [ { "family_name": "Bulfer", "given_name": "Steven", "orcid": "0000-0001-9942-1195" }, { "family_name": "G\u00e1mez", "given_name": "Jorge", "orcid": "0000-0002-9481-4915", "clpid": "Gamez-Jorge" }, { "family_name": "Yan-Huang", "given_name": "Albert", "orcid": "0000-0003-1268-4780" }, { "family_name": "Haghi", "given_name": "Benyamin", "orcid": "0000-0002-4839-7647" }, { "family_name": "Pedroni", "given_name": "Volnei A.", "clpid": "Pedroni-V-A" }, { "family_name": "Andersen", "given_name": "Richard A.", "orcid": "0000-0002-7947-0472", "clpid": "Andersen-R-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "

We present a 192-channel 1D convolutional neural network (1D CNN) based neural feature extractor for Brain-Machine Interfaces (BMI) that achieves state-of-the-art decoding stability at 1.8 μW and 12801 μm2 per channel in 65nm CMOS technology. Our device is a fully configurable, scalable, area and power efficient solution that supports models with 2-8 feature layers and a total kernel length of up to 256. This architecture reduces caching requirements by 5× over conventional computation schemes. Channels and layers are individually power-switchable to further optimize power efficiency for a given neural application. We introduce an on-chip model, FENet-66, that achieves the highest cross-validated decoding performance compared to all previously reported feature sets. We show that this model maintains superior stability over time using recorded data from tetraplegic human participants with spinal cord injury. Our features have 18% higher overall average cross-validated R2 decoding performance compared to Spiking Band Power (SBP), with 28% better performance during the 4th year. Our proposed architecture can also extract mean wavelet power features at low power and latency. We show that custom 1D-CNN kernels achieve 10% better performance compared to wavelet features while compressing the neural data stream by 38×. The models and hardware were validated in real time with a human subject in online closed-loop center-out cursor control experiments with micro-electrode arrays that were implanted for 6 years. Decoders using features generated with this work substantially improve the viability of long-term neural implants compared to other feature extraction methods currently present in low power BMI hardware.

", "doi": "10.1109/tbcas.2025.3615121", "issn": "1932-4545", "publisher": "IEEE", "publication": "IEEE Transactions on Biomedical Circuits and Systems", "publication_date": "2026-02", "series_number": "1", "volume": "20", "issue": "1", "pages": "122 - 136" }, { "id": "authors:qp0pw-qar81", "collection": "authors", "collection_id": "qp0pw-qar81", "cite_using_url": "https://authors.library.caltech.edu/records/qp0pw-qar81", "type": "article", "title": "Continuous biochemical profiling of the gastrointestinal tract using an integrated smart capsule", "author": [ { "family_name": "Min", "given_name": "Jihong", "orcid": "0000-0002-5788-1473", "clpid": "Min-Jihong" }, { "family_name": "Ahn", "given_name": "Hyunah", "orcid": "0000-0002-6345-8559", "clpid": "Ahn-Hyunah" }, { "family_name": "Lukas", "given_name": "Heather", "orcid": "0000-0002-8160-9066", "clpid": "Lukas-Heather-Lauren" }, { "family_name": "Ma", "given_name": "Xiaotian", "orcid": "0009-0000-8357-9916", "clpid": "Ma-Xiaotian" }, { "family_name": "Bhansali", "given_name": "Rinni", "orcid": "0000-0001-6518-5964", "clpid": "Bhansali-Rinni" }, { "family_name": "Sunwoo", "given_name": "Sung-Hyuk", "orcid": "0000-0002-3925-1275", "clpid": "Sunwoo-Sung-Hyuk" }, { "family_name": "Wang", "given_name": "Canran", "clpid": "Wang-Canran" }, { "family_name": "Xu", "given_name": "Yadong", "orcid": "0000-0001-8885-6433", "clpid": "Xu-Yadong" }, { "family_name": "Yao", "given_name": "Dickson R.", "orcid": "0009-0004-8894-8951", "clpid": "Yao-Dickson-Richard" }, { "family_name": "Kim", "given_name": "Gwangmook", "orcid": "0000-0002-7469-408X", "clpid": "Kim-Gwangmook" }, { "family_name": "Li", "given_name": "Zhaoping" }, { "family_name": "Hsiai", "given_name": "Tzung K." }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Jung", "given_name": "Hee-Tae", "orcid": "0000-0002-5727-6732" }, { "family_name": "Gao", "given_name": "Wei", "orcid": "0000-0002-8503-4562", "clpid": "Gao-Wei" } ], "abstract": "The gastrointestinal tract contains a wealth of chemical information that can be used to decipher the health of the digestive and nervous systems. Traditional methods of analysis, such as faecal analysis and biopsies, are invasive, costly and incapable of providing real-time metabolic and hormone profiling across the gastrointestinal tract. Commercial ingestible capsule sensors have been developed, but only monitor basic markers, such as pH and pressure, neglecting detailed chemical analysis. Here we report an integrated smart capsule that can simultaneously detect a spectrum of biochemical markers, including electrolytes, metabolites and hormones. The capsule, which is termed PillTrek, is 7\u2009mm in diameter and 25\u2009mm in length, and houses a miniaturized wireless electrochemical workstation capable of executing a range of electrochemical measurement techniques (potentiometry, amperometry, voltammetry and impedimetry), allowing it to interface with a variety of electrochemical sensors and detect various parameters in the gut. Using an array of sensors (serotonin, glucose, pH, ionic strength and temperature), we illustrate the capabilities of the system in vitro and in vivo in animal studies involving rat and rabbit models, monitoring the dynamic profile of these crucial biomarkers and their responsiveness to different dietary intakes.", "doi": "10.1038/s41928-025-01407-0", "issn": "2520-1131", "publisher": "Nature Publishing Group", "publication": "Nature Electronics", "publication_date": "2025-09", "volume": "8", "pages": "844\u2013855" }, { "id": "authors:1xz93-wgt26", "collection": "authors", "collection_id": "1xz93-wgt26", "cite_using_url": "https://authors.library.caltech.edu/records/1xz93-wgt26", "type": "article", "title": "A Portable Arsenic Sensor Integrating Bacillus megaterium with CMOS Technology", "author": [ { "family_name": "Hu", "given_name": "Chelsea Y.", "orcid": "0000-0002-2211-1778", "clpid": "Hu-Chelsea-Y" }, { "family_name": "McManus", "given_name": "John", "orcid": "0009-0007-7077-0624", "clpid": "McManus-John" }, { "family_name": "Aghlmand", "given_name": "Fatemeh", "orcid": "0000-0002-5103-9314", "clpid": "Aghlmand-Fatemeh" }, { "family_name": "Mei", "given_name": "Tracy", "orcid": "0000-0003-2743-0126" }, { "family_name": "Larsson", "given_name": "Elin", "orcid": "0000-0003-1341-5937", "clpid": "Larsson-Elin" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Murray", "given_name": "Richard M.", "orcid": "0000-0002-5785-7481", "clpid": "Murray-R-M" } ], "abstract": "

Bacteria innately monitor their environment by dynamically regulating gene expression to respond to fluctuating conditions. Through synthetic biology, we can harness this natural capability to design cell-based sensors. Bacillus megaterium, a soil bacterium, stands out due to its remarkable heavy metal tolerance and sporulation ability, making it an ideal candidate for heavy metal detection with low transportation costs. However, challenges persist: the synthetic biology toolkit for this strain is underdeveloped, and conventional whole-cell sensors necessitate specialized laboratory equipment to read the output. In our study, we have genetically modified B. megaterium for arsenic detection and established a detection threshold below the EPA’s recommendation of 10 ppb for drinking water in both vegetative and spore forms. Additionally, we have integrated both engineered B. megaterium living cells and spores with a complementary metal-oxide-semiconductor (CMOS) chip, providing a proof-of-concept for field-deployable arsenic detection. We show that the limit of detection (LOD) of our integrated sensor is within the range to test arsenic levels in soil and food. As a proof of concept, this work paves the way for the deployment of our sensor in resource-limited settings, ensuring real-time arsenic detection in challenging environments.

", "doi": "10.1021/acssynbio.4c00895", "pmcid": "PMC12090344", "issn": "2161-5063", "publisher": "American Chemical Society", "publication": "ACS Synthetic Biology", "publication_date": "2025-05-16", "series_number": "5", "volume": "14", "issue": "5", "pages": "1615-1624" }, { "id": "authors:emwed-ap219", "collection": "authors", "collection_id": "emwed-ap219", "cite_using_url": "https://authors.library.caltech.edu/records/emwed-ap219", "type": "article", "title": "Enhanced control of a brain\u2013computer interface by tetraplegic participants via neural-network-mediated feature extraction", "author": [ { "family_name": "Haghi", "given_name": "Benyamin", "orcid": "0000-0002-4839-7647", "clpid": "Haghi-Benyamin-Allahgholizadeh" }, { "family_name": "Aflalo", "given_name": "Tyson", "orcid": "0000-0002-0101-2455", "clpid": "Aflalo-Tyson" }, { "family_name": "Kellis", "given_name": "Spencer", "orcid": "0000-0002-5158-1058", "clpid": "Kellis-Spencer" }, { "family_name": "Guan", "given_name": "Charles", "orcid": "0000-0002-8040-8844", "clpid": "Guan-Charles" }, { "family_name": "Gamez de Leon", "given_name": "Jorge A.", "clpid": "Gamez-de-Leon-Jorge-A" }, { "family_name": "Huang", "given_name": "Albert Yan", "orcid": "0000-0003-1268-4780", "clpid": "Huang-Albert-Yan" }, { "family_name": "Pouratian", "given_name": "Nader", "clpid": "Pouratian-Nader" }, { "family_name": "Andersen", "given_name": "Richard A.", "orcid": "0000-0002-7947-0472", "clpid": "Andersen-R-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "To infer intent, brain\u2013computer interfaces must extract features that accurately estimate neural activity. However, the degradation of signal quality over time hinders the use of feature-engineering techniques to recover functional information. By using neural data recorded from electrode arrays implanted in the cortices of three human participants, here we show that a convolutional neural network can be used to map electrical signals to neural features by jointly optimizing feature extraction and decoding under the constraint that all the electrodes must use the same neural-network parameters. In all three participants, the neural network led to offline and online performance improvements in a cursor-control task across all metrics, outperforming the rate of threshold crossings and wavelet decomposition of the broadband neural data (among other feature-extraction techniques). We also show that the trained neural network can be used without modification for new datasets, brain areas and participants.", "doi": "10.1038/s41551-024-01297-1", "issn": "2157-846X", "publisher": "Nature Publishing Group", "publication": "Nature Biomedical Engineering", "publication_date": "2024-12-06" }, { "id": "authors:g6zm8-meg23", "collection": "authors", "collection_id": "g6zm8-meg23", "cite_using_url": "https://authors.library.caltech.edu/records/g6zm8-meg23", "type": "article", "title": "A 14.8- \u03bc W Power and < 10 \u03bc T \u1d63\u2098\u209b Noise 3-D AC Magnetic Sensor in CMOS for Biomedical Applications", "author": [ { "family_name": "Sharma", "given_name": "Saransh", "orcid": "0000-0002-5052-4932", "clpid": "Sharma-Saransh" }, { "family_name": "Melton", "given_name": "Hayward", "clpid": "Melton-Hayward-J" }, { "family_name": "Edmonds", "given_name": "Liliana B.", "orcid": "0000-0002-2068-3334" }, { "family_name": "Addington", "given_name": "Olivia", "clpid": "Addington-Olivia" }, { "family_name": "Shapiro", "given_name": "Mikhail G.", "orcid": "0000-0002-0291-4215", "clpid": "Shapiro-M-G" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "

Magnetic sensors are used extensively in applications related to automotives, navigation, medical electronics, and consumer products. Hall sensors are commonly used due to their compatibility with the standard CMOS process but suffer from poor 3-D sensitivity and consume high power. Here, we present the first-of-its-kind 3-D ac magnetic sensor in the CMOS process with high-resolution and ultralow-power operation. The sensor is comprised of three orthogonal and highly dense metal coils ( X , Y , and Z ) implemented in the 65-nm node, which generate a voltage in response to ac magnetic fields by electromagnetic induction. The X and Y sensor coils are realized in the vertical plane of the CMOS chip by using interconnect vias as part of the coil structure, while the Z sensor is realized in the horizontal plane. The induced voltage by the three coils is processed by a low-noise instrumentation amplifier (IA), sharp bandpass filter (BPF), programmable gain amplifier (PGA), differential peak detect and hold circuit, 12-bit successive approximation register (SAR) analog-to-digital converter (ADC), and serializer. The entire circuitry consumes only 14.8 μ W to yield μ T-level resolution. The sensor is successfully demonstrated for 3-D localization and tracking of catheters with 500- μ m mean accuracy in a surgical operation room (OR), which shows significant potential toward clinical translation.

", "doi": "10.1109/jssc.2024.3482268", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2024-10-31", "pages": "1-12" }, { "id": "authors:mv6x4-p4n12", "collection": "authors", "collection_id": "mv6x4-p4n12", "cite_using_url": "https://authors.library.caltech.edu/records/mv6x4-p4n12", "type": "conference_item", "title": "Holistic Co-Design of Electronics and Photonics for High-Speed Optical Interconnects in SiP and CMOS Platforms", "book_title": "2024 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Talkhooncheh", "given_name": "Arian Hashemi", "orcid": "0000-0001-8946-5047", "clpid": "Talkhooncheh-Arian-Hashemi" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "
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Data centers continue to demand interconnect solutions with increasingly higher bandwidth densities and improved energy efficiency, both for connections within and between data centers. Furthermore, applications such as chip-to-chip interconnects in data center switches, high-performance field programmable gate arrays (FPGAs), and graphics processing units (GPUs) call for compact form-factors, high-volume production and low-cost. Silicon Photonics (SiP)-based transceivers, when co-packaged with CMOS electronics, offer a promising avenue to meet these demands with speeds exceeding 100 Gb/s per wavelength. Additionally, they have the capability to support higher-order modulation schemes in the optical domain, such as multilevel Pulse Amplitude Modulation (PAM-N) and Multi-point Quadrature-Amplitude Modulation (QAM-N) schemes, thereby enhancing bandwidth densities. Achieving improved electro-optical bandwidth density while maintaining optimized power efficiency necessitates addressing the optical power penalty associated with photonic integrated circuits. Furthermore, the co-optimization of electronic and photonic components provides a pathway towards achieving sub-pJ/b transmission efficiency.
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", "doi": "10.1109/cicc60959.2024.10529057", "isbn": "979-8-3503-9406-1", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2024-04", "pages": "1-8" }, { "id": "authors:1fpbq-zba19", "collection": "authors", "collection_id": "1fpbq-zba19", "cite_using_url": "https://authors.library.caltech.edu/records/1fpbq-zba19", "type": "conference_item", "title": "EKGNet: A 10.96\u03bcW Fully Analog Neural Network for Intra-Patient Arrhythmia Classification", "book_title": "2023 IEEE Biomedical Circuits and Systems Conference (BioCAS)", "author": [ { "family_name": "Haghi", "given_name": "Benyamin", "orcid": "0000-0002-4839-7647", "clpid": "Haghi-Benyamin-Allahgholizadeh" }, { "family_name": "Ma", "given_name": "Lin", "clpid": "Ma-Lin" }, { "family_name": "Lale", "given_name": "Sahin", "orcid": "0000-0002-7191-346X", "clpid": "Lale-Sahin" }, { "family_name": "Anandkumar", "given_name": "Anima", "orcid": "0000-0002-6974-6797", "clpid": "Anandkumar-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "
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We present an integrated approach by combining analog computing and deep learning for electrocardiogram (ECG) arrythmia classification. We propose EKGNet, a hardware-efficient and fully analog arrythmia classification architecture that achieves high accuracy with low power consumption. The proposed architecture leverages the energy efficiency of transistors operating in the subthreshold region, eliminating the need for analog-to-digital converters (ADC) and static random-access memory (SRAM). The system design includes a novel analog sequential Multiply-Accumulate (MAC) circuit that mitigates process, supply voltage, and temperature variations. Experimental evaluations on PhysionNet’s MIT-BIH and PTB Diagnostics datasets demonstrate the effectiveness of the proposed method, achieving an average balanced accuracies of 95% and 94.25% for intra-patient arrhythmia classification and myocardial infarction (MI) classification, respectively. This innovative approach presents a promising avenue for developing low power arrythmia classification systems with enhanced accuracy and transferability in biomedical applications.
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", "doi": "10.1109/biocas58349.2023.10389164", "isbn": "979-8-3503-0026-0", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2023-10", "pages": "1-5" }, { "id": "authors:9b1s3-3cn39", "collection": "authors", "collection_id": "9b1s3-3cn39", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20230526-663046000.25", "type": "book_section", "title": "A Monolithic 3D Magnetic Sensor in 65nm CMOS with <10\u03bcTrms Noise and 14.8\u03bcW Power", "book_title": "2023 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Sharma", "given_name": "Saransh", "orcid": "0000-0002-5052-4932", "clpid": "Sharma-Saransh" }, { "family_name": "Melton", "given_name": "Hayward", "clpid": "Melton-Hayward" }, { "family_name": "Edmonds", "given_name": "Liliana", "orcid": "0000-0002-2068-3334", "clpid": "Edmonds-Liliana" }, { "family_name": "Addington", "given_name": "Olivia", "clpid": "Addington-Olivia" }, { "family_name": "Shapiro", "given_name": "Mikhail", "orcid": "0000-0002-0291-4215", "clpid": "Shapiro-M-G" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Magnetic sensors have become increasingly ubiquitous as they constitute an integral part of several fast-growing sectors such as automotive, navigation, robotics, medical devices and consumer electronics. Due to their compatibility with the standard CMOS process, Hall magnetic sensors are widely used. However, one of the key challenges of CMOS-based Hall sensors is their relatively low sensitivity, which is inevitable given the low Hall coefficient of Si. For better sensitivity, Hall sensors are biased at higher current levels which hinders their widescale use in low-power bioelectronics and other power-constrained applications. Another challenge is the difficulty in implementing high-sensitivity vertical Hall elements in planar CMOS processes for 3D sensing. This is often overcome by using ferromagnetic materials that require additional and expensive steps during fabrication, thus increasing the cost.", "doi": "10.1109/cicc57935.2023.10121313", "isbn": "9798350399486", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2023-04" }, { "id": "authors:n3gje-t4y22", "collection": "authors", "collection_id": "n3gje-t4y22", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20230214-651108000.1", "type": "article", "title": "Location-aware ingestible microdevices for wireless monitoring of gastrointestinal dynamics", "author": [ { "family_name": "Sharma", "given_name": "Saransh", "orcid": "0000-0002-5052-4932", "clpid": "Sharma-Saransh" }, { "family_name": "Ramadi", "given_name": "Khalil B.", "clpid": "Ramadi-Khalil-B" }, { "family_name": "Poole", "given_name": "Nikhil H.", "clpid": "Poole-Nikhil-H" }, { "family_name": "Srinivasan", "given_name": "Shriya S.", "orcid": "0000-0002-2508-1324", "clpid": "Srinivasan-Shriya-S" }, { "family_name": "Ishida", "given_name": "Keiko", "orcid": "0000-0003-0894-296X", "clpid": "Ishida-Keiko" }, { "family_name": "Kuosmanen", "given_name": "Johannes", "clpid": "Kuosmanen-Johannes" }, { "family_name": "Jenkins", "given_name": "Josh", "orcid": "0000-0001-7698-9888", "clpid": "Jenkins-Joshua" }, { "family_name": "Aghlmand", "given_name": "Fatemeh", "orcid": "0000-0002-5103-9314", "clpid": "Aghlmand-Fatemeh" }, { "family_name": "Swift", "given_name": "Margaret B.", "orcid": "0000-0001-9610-0687", "clpid": "Swift-Margaret-B" }, { "family_name": "Shapiro", "given_name": "Mikhail G.", "orcid": "0000-0002-0291-4215", "clpid": "Shapiro-M-G" }, { "family_name": "Traverso", "given_name": "Giovanni", "orcid": "0000-0001-7851-4077", "clpid": "Traverso-Giovanni" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Localization and tracking of ingestible microdevices in the gastrointestinal (GI) tract is valuable for the diagnosis and treatment of GI disorders. Such systems require a large field-of-view of tracking, high spatiotemporal resolution, wirelessly operated microdevices and a non-obstructive field generator that is safe to use in practical settings. However, the capabilities of current systems remain limited. Here, we report three dimensional (3D) localization and tracking of wireless ingestible microdevices in the GI tract of large animals in real time and with millimetre-scale resolution. This is achieved by generating 3D magnetic field gradients in the GI field-of-view using high-efficiency planar electromagnetic coils that encode each spatial point with a distinct magnetic field magnitude. The field magnitude is measured and transmitted by the miniaturized, low-power and wireless microdevices to decode their location as they travel through the GI tract. This system could be useful for quantitative assessment of the GI transit-time, precision targeting of therapeutic interventions and minimally invasive procedures.", "doi": "10.1038/s41928-023-00916-0", "pmcid": "PMC10516531", "issn": "2520-1131", "publisher": "Nature Publishing Group", "publication": "Nature Electronics", "publication_date": "2023-03", "series_number": "3", "volume": "6", "issue": "3", "pages": "242-256" }, { "id": "authors:40smm-8cd68", "collection": "authors", "collection_id": "40smm-8cd68", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20230227-664835000.2", "type": "article", "title": "A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators", "author": [ { "family_name": "Hashemi Talkhooncheh", "given_name": "Arian", "orcid": "0000-0001-8946-5047", "clpid": "Hashemi-Talkhooncheh-Arian" }, { "family_name": "Zhang", "given_name": "Weiwei", "orcid": "0000-0002-1086-5775", "clpid": "Zhang-Weiwei" }, { "family_name": "Wang", "given_name": "Minwo", "clpid": "Wang-Minwo" }, { "family_name": "Thomson", "given_name": "David J.", "orcid": "0000-0002-1838-2663", "clpid": "Thomson-David-J" }, { "family_name": "Ebert", "given_name": "Martin", "clpid": "Ebert-Martin" }, { "family_name": "Ke", "given_name": "Li", "orcid": "0000-0002-2954-1383", "clpid": "Ke-Li" }, { "family_name": "Reed", "given_name": "Graham T.", "clpid": "Reed-Graham-T" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This article presents a 100-Gb/s four-level pulse-amplitude modulation (PAM4) optical transmitter system implemented in a 3-D-integrated silicon photonics-CMOS platform. The photonics chip includes a push\u2013pull segmented Mach\u2013Zehnder modulator (MZM) structure using highly capacitive (415 fF\u20131.1 pF), yet optically efficient ( V_\u03c0L=0.8V\u22c5 cm) metal\u2013oxide\u2013silicon capacitor (MOSCAP) phase modulators. Two pairs of U-shaped modulator segments with effective lengths of 170 and 450 \u03bcm are driven at 50 GBd by a dual-channel 28-nm CMOS driver, which is flip-chip bonded to the photonics chip. The driver cores utilize digitally controllable pre-distortion (PD) and inductive peaking to achieve sufficient electro-optical bandwidth (EOBW). The drivers deliver 1.2-Vppd swing to modulators using a 0.9-V supply and on-chip serializers that generate 50-Gb/s data streams. The electronics chip consumes 240 mW achieving 2.4-pJ/bit energy efficiency. The overall EOBW, without any PD, is increased by approximately 56% and 48% for the 170- and 450- \u03bcm segments, respectively, when compared to their EOBW measured by 65-GHz 50-\u03a9 terminated probes. The optical input power to the photonics chip is +10 dBm, and an erbium-doped fiber amplifier amplifies output signals by 11 dB. The 50-Gb/s nonreturn to zero (NRZ) optical raw eye diagram exhibits 4.3-dB extinction ratio (ER) and 1.2 dBm of optical modulation amplitude (OMA). The 100-Gb/s PAM4 optical raw eye diagram shows 4.3-dB ER and 1.4-dBm OMA with a transmitter dispersion eye closure quaternary (TDECQ) of 1.53 dB after a five-tap feed-forward-equalization (FFE) filter. The PAM4 TDECQ changes by 53% when the temperature is increased from 30 \u00b0C to 90 \u00b0C at the optimum forward bias voltage of 1 V.", "doi": "10.1109/jssc.2022.3210906", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2023-01", "series_number": "1", "volume": "58", "issue": "1", "pages": "30-44" }, { "id": "authors:656q7-h5r84", "collection": "authors", "collection_id": "656q7-h5r84", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20220407-668501590", "type": "article", "title": "A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS", "author": [ { "family_name": "Uran", "given_name": "Arda", "orcid": "0000-0002-8762-4494", "clpid": "Uran-Arda" }, { "family_name": "Ture", "given_name": "Kerim", "orcid": "0000-0003-3531-140X", "clpid": "Ture-Kerim" }, { "family_name": "Aprile", "given_name": "Cosimo", "orcid": "0000-0002-6558-7688", "clpid": "Aprile-Cosimo" }, { "family_name": "Trouillet", "given_name": "Alix", "orcid": "0000-0002-4242-0324", "clpid": "Trouillet-Alix" }, { "family_name": "Fallegger", "given_name": "Florian", "orcid": "0000-0003-0626-5264", "clpid": "Fallegger-Florian" }, { "family_name": "Revol", "given_name": "Emilie C. M.", "orcid": "0000-0002-8483-2239", "clpid": "Revol-Emilie-C-M" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Lacour", "given_name": "St\u00e9phanie P.", "clpid": "Lacour-St\u00e9phanie-P" }, { "family_name": "Dehollain", "given_name": "Catherine", "orcid": "0000-0002-6262-2644", "clpid": "Dehollain-Catherine" }, { "family_name": "Leblebici", "given_name": "Yusuf", "clpid": "Leblebici-Yusuf" }, { "family_name": "Cevher", "given_name": "Volkan", "clpid": "Cevher-Volkan" } ], "abstract": "Next-generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this article presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. Energy-area-efficient 10-bit 20-kS/s front end amplifies and digitizes the neural signals within the local field potential (LFP) and action potential (AP) bands. The raw data from each channel are decomposed into spectral features using a compressed Hadamard transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and off-line experiments. The prototype fabricated in 65-nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overall signal chain consumes 2.6 \u03bcW and occupies 0.021 mm\u00b2 per channel, pointing toward its feasibility for 1000-channel single-die neural recording systems.", "doi": "10.1109/jssc.2022.3161296", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2022-04-07" }, { "id": "authors:rr4bx-nz318", "collection": "authors", "collection_id": "rr4bx-nz318", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20220407-503740421", "type": "book_section", "title": "A 2.4pJ/b 100Gb/s 3D-integrated PAM-4 Optical Transmitter with Segmented SiP MOSCAP Modulators and a 2-Channel 28nm CMOS Driver", "book_title": "2022 IEEE International Solid- State Circuits Conference (ISSCC)", "author": [ { "family_name": "Hashemi Talkhooncheh", "given_name": "Arian", "orcid": "0000-0001-8946-5047", "clpid": "Hashemi-Talkhooncheh-Arian" }, { "family_name": "Zhang", "given_name": "Weiwei", "orcid": "0000-0002-1086-5775", "clpid": "Zhang-Weiwei" }, { "family_name": "Wang", "given_name": "Minwo", "clpid": "Wang-Minwo" }, { "family_name": "Thomson", "given_name": "David J.", "orcid": "0000-0002-1838-2663", "clpid": "Thomson-David-J" }, { "family_name": "Ebert", "given_name": "Martin", "clpid": "Ebert-Martin" }, { "family_name": "Ke", "given_name": "Li", "clpid": "Ke-Li" }, { "family_name": "Reed", "given_name": "Graham T.", "clpid": "Reed-Graham-T" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Data centers continue to require interconnects with higher bandwidth densities and energy efficiencies. Silicon photonics (SiP)-based solutions have gained interest for implementing low-cost and power efficient 100+Gb/s/A optical transceivers. While microring modulators (MRMs) have small footprints and high electro-optical bandwidth (EOBW), they suffer from an inherent tradeoff between bandwidth and optical phase efficiency, high sensitivity to process and temperature variations, and non-linear electro-optic characteristics [1 \u2013 2]. Travelling-wave Mach-Zehnder Modulators (TW-MZMs) require power-hungry drivers to compensate microwave losses and occupy large areas on chip [3 \u2013 4]. Metal-oxide-silicon-capacitor (MOSCAP)-based phase modulators can significantly scale the area and power of the optical transmitter (OTX) owing to their superior optical efficiency (voltage-length product at n phase shift of V \u03c0 L < 1Vmm) and compact footprint (< 1mm) [5]. MOSCAP modulators, however, impose large capacitive parasitics (~3fF/\u03bcm), which could limit the electro-optical bandwidth (EOBW) significantly. State-of-the-art wireline transmitters cannot meet the requirements of MOSCAP modulators due to their 50\u03a9-terminated design and limited output voltage swing [6]. This paper presents a 3D-integrated 100Gb/s PAM-4 OTX with electronic pre-distortion (PD) and BW extension techniques to compensate for MOSCAP modulator BW limitations.", "doi": "10.1109/isscc42614.2022.9731563", "isbn": "9781665428002", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2022-02", "pages": "284-286" }, { "id": "authors:0fstm-jw173", "collection": "authors", "collection_id": "0fstm-jw173", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20220105-20825500", "type": "book_section", "title": "A 100 Gb/s PAM-4 Silicon Photonic Transmitter with Two Binary-Driven EAMs in MZI Structure", "book_title": "2021 IEEE Photonics Conference (IPC)", "author": [ { "family_name": "Talkhooncheh", "given_name": "Arian Hashemi", "orcid": "0000-0001-8946-5047", "clpid": "Talkhooncheh-Arian-Hashemi" }, { "family_name": "Zilkie", "given_name": "Aaron", "clpid": "Zilkie-Aaron" }, { "family_name": "Yu", "given_name": "Guomin", "clpid": "Yu-Guomin" }, { "family_name": "Shafiiha", "given_name": "Roshanak", "clpid": "Shafiiha-Roshanak" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "An integrated DAC-less PAM-4 transmitter in a multi-micron silicon photonics platform using 2 binary-driven uneven-length SiGe EAMs in an unbalanced MZI is presented. The optical transmitter exhibits 5.5dB ER at 100 Gb/s with 2.1dB SNR improvement compared to single EAMs driven by PAM-4 signals.", "doi": "10.1109/ipc48725.2021.9593028", "isbn": "978-1-6654-1601-6", "publisher": "IEEE", "publication_date": "2021-10", "pages": "1-2" }, { "id": "authors:rfgy5-j8882", "collection": "authors", "collection_id": "rfgy5-j8882", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20220105-126541900", "type": "book_section", "title": "Nonlinear Equalization for Optical Interconnects", "book_title": "2021 IEEE Photonics Conference (IPC)", "author": [ { "family_name": "Chen", "given_name": "Kuan-Chang", "orcid": "0000-0003-2968-4656", "clpid": "Chen-Kuan-Chang" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper focuses on nonlinearity compensation schemes for optical interconnects. Receiver-side digital nonlinear equalizers are investigated, and a custom piecewise-linear equalizer is proposed as an energy-efficient candidate. Transmitter-side techniques utilizing nonlinear electrical drivers or segmented optical modulators are reviewed.", "doi": "10.1109/ipc48725.2021.9593017", "isbn": "978-1-6654-1601-6", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2021-10", "pages": "1-2" }, { "id": "authors:1ka0f-tfw77", "collection": "authors", "collection_id": "1ka0f-tfw77", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20210409-105849791", "type": "article", "title": "Wireless 3D Surgical Navigation and Tracking System With 100\u03bcm Accuracy Using Magnetic-Field Gradient-Based Localization", "author": [ { "family_name": "Sharma", "given_name": "Saransh", "orcid": "0000-0002-5052-4932", "clpid": "Sharma-Saransh" }, { "family_name": "Telikicherla", "given_name": "Aditya", "clpid": "Telikicherla-Aditya" }, { "family_name": "Ding", "given_name": "Grace", "orcid": "0000-0002-0484-3385", "clpid": "Ding-Grace" }, { "family_name": "Aghlmand", "given_name": "Fatemeh", "orcid": "0000-0002-5103-9314", "clpid": "Aghlmand-Fatemeh" }, { "family_name": "Talkhooncheh", "given_name": "Arian Hashemi", "orcid": "0000-0001-8946-5047", "clpid": "Talkhooncheh-Arian-Hashemi" }, { "family_name": "Shapiro", "given_name": "Mikhail G.", "orcid": "0000-0002-0291-4215", "clpid": "Shapiro-M-G" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper describes a high-resolution 3D navigation and tracking system using magnetic field gradients, that can replace X-Ray fluoroscopy in high-precision surgeries. Monotonically varying magnetic fields in X, Y and Z directions are created in the field-of-view (FOV) to produce magnetic field gradients, which encode each spatial point uniquely. Highly miniaturized, wireless and battery-less devices, capable of measuring their local magnetic field, are designed to sense the gradient field. One such device can be attached to an implant inside the body and another to a surgical tool, such that both can simultaneously measure and communicate the magnetic field at their respective locations to an external receiver. The relative location of the two devices on a real-time display can enable precise surgical navigation without using X-Rays. A prototype device is designed consisting of a micro-chip fabricated in 65nm CMOS technology, a 3D magnetic sensor and an inductor-coil. Planar electromagnetic coils are designed for creating the 3D magnetic field gradients in a 20 \u00d7 20 \u00d7 10cm\u00b3 of scalable FOV. Unambiguous and orientation-independent spatial encoding is achieved by: (i) using the gradient in the total field magnitude instead of only the Z-component; and (ii) using a combination of the gradient fields to correct for the non-linearity and non-monotonicity in X and Y gradients. The resultant X and Y FOV yield \u226590% utilization of their respective coil-span. The system is tested in vitro to demonstrate a localization accuracy of <100 \u03bcm in 3D, the highest reported to the best of our knowledge.", "doi": "10.1109/tmi.2021.3071120", "issn": "0278-0062", "publisher": "IEEE", "publication": "IEEE Transactions on Medical Imaging", "publication_date": "2021-08", "series_number": "8", "volume": "40", "issue": "8", "pages": "2066-2079" }, { "id": "authors:a4w22-5s845", "collection": "authors", "collection_id": "a4w22-5s845", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20210528-094923310", "type": "book_section", "title": "A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS", "book_title": "2021 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Uran", "given_name": "Arda", "orcid": "0000-0002-8762-4494", "clpid": "Uran-Arda" }, { "family_name": "Ture", "given_name": "Kerim", "clpid": "Ture-Kerim" }, { "family_name": "Aprile", "given_name": "Cosimo", "clpid": "Aprile-Cosimo" }, { "family_name": "Trouillet", "given_name": "Alix", "clpid": "Trouillet-Alix" }, { "family_name": "Fallegger", "given_name": "Florian", "clpid": "Fallegger-Florian" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Lacour", "given_name": "Stephanie P.", "clpid": "Lacour-Stephanie-P" }, { "family_name": "Dehollain", "given_name": "Catherine", "clpid": "Dehollain-Catherine" }, { "family_name": "Leblebici", "given_name": "Yusuf", "clpid": "Leblebici-Yusuf" }, { "family_name": "Cevher", "given_name": "Volkan", "clpid": "Cevher-Volkan" } ], "abstract": "Wireless implantable neural recording chips enable multichannel data acquisition with high spatiotemporal resolution in situ. Recently, the use of machine learning approaches on neural data for diagnosis and prosthesis control have renewed the interest in this field, and increased even more the demand for multichannel data. However, simultaneous data acquisition from many channels is a grand challenge due to data rate and power limitations on wireless transmission for implants. As a result, recent studies have focused on on-chip classifiers (Fig. 1 top), despite the fact that only primitive classifiers can be placed on resource-constrained chips. Moreover, robustness of the chosen algorithm cannot be guaranteed pre-implantation due to the scarcity of patient-specific data; waveforms can change over time due to electrode micro migration or tissue reaction, highlighting the need for robust adaptive features.", "doi": "10.1109/cicc51472.2021.9431458", "isbn": "9781728175812", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2021-04", "pages": "Art. No. 10-4" }, { "id": "authors:ya9qy-vj688", "collection": "authors", "collection_id": "ya9qy-vj688", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20201120-095702860", "type": "article", "title": "A Biofuel-Cell-Based Energy Harvester With 86% Peak Efficiency and 0.25-V Minimum Input Voltage Using Source-Adaptive MPPT", "author": [ { "family_name": "Talkhooncheh", "given_name": "Arian Hashemi", "orcid": "0000-0001-8946-5047", "clpid": "Talkhooncheh-Arian-Hashemi" }, { "family_name": "Yu", "given_name": "You", "orcid": "0000-0001-7059-7023", "clpid": "Yu-You" }, { "family_name": "Agarwal", "given_name": "Abhinav", "clpid": "Agarwal-Abhinav" }, { "family_name": "Kuo", "given_name": "William Wei-Ting", "clpid": "Kuo-William-Wei-Ting" }, { "family_name": "Chen", "given_name": "Kuan-Chang", "orcid": "0000-0003-2968-4656", "clpid": "Chen-Kuan-Chang" }, { "family_name": "Wang", "given_name": "Minwo", "clpid": "Wang-Minwo" }, { "family_name": "Hoskuldsdottir", "given_name": "Gudrun", "clpid": "Hoskuldsdottir-Gudrun" }, { "family_name": "Gao", "given_name": "Wei", "orcid": "0000-0002-8503-4562", "clpid": "Gao-Wei" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This article presents an efficient cold-starting energy harvester system, fabricated in 65-nm CMOS. The proposed harvester uses no external electrical components and is compatible with biofuel-cell (BFC) voltage and power ranges. A power-efficient system architecture is proposed to keep the internal circuitry operating at 0.4 V while regulating the output voltage at 1 V using switched-capacitor dc\u2013dc converters and a hysteretic controller. A startup enhancement block is presented to facilitate cold startup with any arbitrary input voltage. A real-time on-chip 2-D maximum power point tracking with source degradation tracing is also implemented to maintain power efficiency maximized over time. The system performs cold startup with a minimum input voltage of 0.39 V and continues its operation if the input voltage degrades to as low as 0.25 V. Peak power efficiency of 86% is achieved at 0.39 V of input voltage and 1.34 \u03bcW of output power with 220 nW of average power consumption of the chip. The end-to-end power efficiency is kept above 70% for a wide range of loading powers from 1 to 12 \u03bcW. The chip is integrated with a pair of lactate BFC electrodes with 2 mm of diameter on a prototype-printed circuit board (PCB). Integrated operation of the chip with the electrodes and a lactate solution is demonstrated.", "doi": "10.1109/jssc.2020.3035491", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2021-03", "series_number": "3", "volume": "56", "issue": "3", "pages": "715-728" }, { "id": "authors:4bedn-e0767", "collection": "authors", "collection_id": "4bedn-e0767", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20201008-083808739", "type": "article", "title": "A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS", "author": [ { "family_name": "Chen", "given_name": "Kuan-Chang", "orcid": "0000-0003-2968-4656", "clpid": "Chen-Kuan-Chang" }, { "family_name": "Kuo", "given_name": "William Wei-Ting", "clpid": "Kuo-William-Wei-Ting" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This article describes a 4-level pulse amplitude modulation (PAM4) receiver incorporating continuous time linear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer (DFE) for applications in wireline communication. A CMOS track-and-regenerate slicer is proposed and employed in the PAM4 receiver. The proposed slicer is designed for the purposes of improving the clock-to-Q delay as well as the output signal swing. A direct DFE in a PAM4 receiver is made possible with the proposed slicer by having rail-to-rail digital feedback signals available with reduced delay, and accordingly relaxing the settling time constraint of the summer. With the 2-tap direct DFE enabled by the proposed slicer, loop-unrolling and inductor-based bandwidth enhancement techniques, which can be area/power intensive, are not necessary at high data rates. The PAM4 receiver fabricated in 28-nm CMOS technology achieves bit-error-rate (BER) better than 1E-12, and energy efficiency of 1.1 pJ/b at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist.", "doi": "10.1109/jssc.2020.3025285", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2021-03", "series_number": "3", "volume": "56", "issue": "3", "pages": "750-762" }, { "id": "authors:6x8nd-s6543", "collection": "authors", "collection_id": "6x8nd-s6543", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20210209-153207262", "type": "book_section", "title": "An 8Gbps Adaptive Receiver for RF over FSO in 28nm CMOS", "book_title": "Proceedings of the 15th European Microwave Integrated Circuits Conference", "author": [ { "family_name": "Aghlmand", "given_name": "Fatemeh", "clpid": "Aghlmand-Fatemeh" }, { "family_name": "Sharma", "given_name": "Saransh", "orcid": "0000-0002-5052-4932", "clpid": "Sharma-Saransh" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a fully integrated high-bandwidth receiver for RF-over-free-space optics (RoFSO). Using subcarrier intensity modulation (SIM) and direct detection scheme, high data rate optical communication is supported in a high-loss atmospheric channel. For proof-of-concept demonstration, an 8Gbps input data via differential phase shift keying (DPSK) modulation and with 10GHz of RF bandwidth is employed. The link performance is assessed by exposing the system to more than 26dB of optical loss equivalent to 3.5km of free space distance under moderate visibility conditions. The receiver chip uses adaptive control loops to compensate for the atmospheric effects and extends the dynamic range. It has been designed and implemented in 28nm CMOS process and achieves 58dB of gain and 18GHz of bandwidth.", "doi": "10.1109/EuMIC48047.2021.00024", "isbn": "978-1-7281-7040-4", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2021-01", "pages": "49-52" }, { "id": "authors:dfv27-n6x40", "collection": "authors", "collection_id": "dfv27-n6x40", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20200806-153947821", "type": "article", "title": "An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm\u00b2 \u00d7 fJ/conv-step Efficiency and 0.97 NEF", "author": [ { "family_name": "Uran", "given_name": "Arda", "orcid": "0000-0002-8762-4494", "clpid": "Uran-Arda" }, { "family_name": "Leblebici", "given_name": "Yusuf", "clpid": "Leblebici-Yusuf" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Cevher", "given_name": "Volkan", "clpid": "Cevher-V" } ], "abstract": "This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local field and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves 4\u00d7 smaller area and 3\u00d7 higher energy\u2013area efficiency compared to the state of the art with 164 \u03bcm\u00d740\u03bcm footprint and 0.78 mm\u00b2\u00d7 fJ/conv-step energy-area figure of merit. The measured 0.65- \u03bcW power consumption and 3.1 - \u03bcVrms input-referred noise within 1 Hz\u201310 kHz bandwidth correspond to a noise efficiency factor of 0.97.", "doi": "10.1109/lssc.2020.3013993", "issn": "2573-9603", "publisher": "IEEE", "publication": "IEEE Solid-State Circuits Letters", "publication_date": "2020-08-04", "volume": "3", "pages": "258-261" }, { "id": "authors:x5gpd-3c682", "collection": "authors", "collection_id": "x5gpd-3c682", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20200430-151240868", "type": "book_section", "title": "A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS", "book_title": "2020 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Chen", "given_name": "Kuan-Chang", "orcid": "0000-0003-2968-4656", "clpid": "Chen-Kuan-Chang" }, { "family_name": "Kuo", "given_name": "William Wei-Ting", "clpid": "Kuo-William-Wei-Ting" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper describes a 4-level pulse-amplitude modulation (PAM4) wireline receiver incorporating a continuous time linear equalizer (CTLE) and a 2-tap direct decision feedback equalizer (DFE). A track-and-regenerate CMOS slicer is proposed and employed in the PAM4 receiver. The reduced delay of the proposed slicer and its full-swing outputs allow the implementation of 2-tap direct decision-feedback equalization at 60-Gb/s with improved energy efficiency and area requirements. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieved BER better than 1E-12 at 60-Gb/s with 1.1 pJ/b energy efficiency measured over a channel of 8.2dB loss at Nyquist rate.", "doi": "10.1109/cicc48029.2020.9075948", "isbn": "9781728160313", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2020-03", "pages": "1-4" }, { "id": "authors:yxqmq-aaf07", "collection": "authors", "collection_id": "yxqmq-aaf07", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20200430-151240979", "type": "book_section", "title": "A Fully-Integrated Biofuel-Cell-Based Energy Harvester with 86% Peak Efficiency and 0.25V Minimum Input Voltage Using Source-Adaptive MPPT", "book_title": "2020 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Talkhooncheh", "given_name": "Arian Hashemi", "clpid": "Talkhooncheh-A-H" }, { "family_name": "Yu", "given_name": "You", "orcid": "0000-0001-7059-7023", "clpid": "Yu-You" }, { "family_name": "Agarwal", "given_name": "Abhinav", "clpid": "Agarwal-Abhinav" }, { "family_name": "Kuo", "given_name": "William", "clpid": "Kuo-William-Wei-Ting" }, { "family_name": "Chen", "given_name": "Kuan-Chang Xavier", "clpid": "Chen-Kuan-Chang-Xavier" }, { "family_name": "Wang", "given_name": "Minwo", "clpid": "Wang-Minwo" }, { "family_name": "Hoskuldsdottir", "given_name": "Gudrun", "clpid": "Hoskuldsdottir-Gudrun" }, { "family_name": "Gao", "given_name": "Wei", "orcid": "0000-0002-8503-4562", "clpid": "Gao-Wei" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a cold-starting energy harvester in 65nm CMOS with source degradation tracking and automatic MPPT. A power-efficient architecture is proposed to keep the internal circuitry operating at 0.4V while regulating the output voltage at 1V using switched-capacitor DC-DC converters and a hysteresis controller. Peak efficiency of 86% is achieved at 0.39V input voltage and 1.34\u03bcW of output power with 220nW of internal average power consumption. Integrated operation with lactate biofuel cells is demonstrated.", "doi": "10.1109/cicc48029.2020.9075912", "isbn": "9781728160313", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2020-03", "pages": "1-4" }, { "id": "authors:9qzyb-cv806", "collection": "authors", "collection_id": "9qzyb-cv806", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20200417-102219007", "type": "book_section", "title": "3D Surgical Alignment with 100\u00b5m Resolution Using Magnetic-Field Gradient-Based Localization", "book_title": "2020 IEEE International Solid-State Circuits Conference", "author": [ { "family_name": "Sharma", "given_name": "Saransh", "clpid": "Sharma-S" }, { "family_name": "Ding", "given_name": "Grace", "clpid": "Ding-Grace" }, { "family_name": "Telikicherla", "given_name": "Aditya", "clpid": "Telikicherla-A" }, { "family_name": "Aghlmand", "given_name": "Fatemeh", "clpid": "Aghlmand-F" }, { "family_name": "Talkhooncheh", "given_name": "Arian Hashemi", "clpid": "Talkhooncheh-A-H" }, { "family_name": "Wang", "given_name": "Minwo", "clpid": "Wang-Minwo" }, { "family_name": "Shapiro", "given_name": "Mikhail G.", "orcid": "0000-0002-0291-4215", "clpid": "Shapiro-M-G" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Substantial advances in the field of surgery have taken place in recent years, which aim at decreasing patient morbidity through innovations in endoscopy, optical imaging, laparoscopic and robotic technologies. However, real-time imaging and navigation during high precision surgery necessitates the use of X-Ray fluoroscopy with most existing technologies to achieve precise localization. Intramedullary (IM) nailing is a common example of such high precision orthopedic surgery, which requires insertion of a nail into the medullary canal of a fractured bone followed by locking screws [1]. Proximal screw locking is performed using a mechanical guide, which is not possible for distal locking owing to the deformation (\u224815mm) caused during insertion [2]. Freehand technique is typically used to localize distal holes, in which the surgical drill is aligned with the hole axis through fluoroscopic imaging. This process is time-consuming and exposes the patient and surgical team to high ionizing radiation. Various other methods, which reduce or eliminate irradiation during distal locking, are not widely used. This is attributed to their lack of compensation for significant deformation of the nail, added requirements such as computing systems, extra robotic arms, CT images, sophisticated hardware and software that require training for the surgeon and staff.", "doi": "10.1109/isscc19947.2020.9063108", "isbn": "9781728132051", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2020-02", "pages": "318-320" }, { "id": "authors:b72n6-64504", "collection": "authors", "collection_id": "b72n6-64504", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190724-154847448", "type": "book_section", "title": "Deep Multi-State Dynamic Recurrent Neural Networks Operating on Wavelet Based Neural Features for Robust Brain Machine Interfaces", "author": [ { "family_name": "Haghi", "given_name": "Benyamin", "orcid": "0000-0002-4839-7647", "clpid": "Haghi-B-A" }, { "family_name": "Kellis", "given_name": "Spencer", "orcid": "0000-0002-5158-1058", "clpid": "Kellis-Spencer-S" }, { "family_name": "Shah", "given_name": "Sahil", "clpid": "Shah-Sahil" }, { "family_name": "Ashok", "given_name": "Maitreyi", "clpid": "Ashok-M" }, { "family_name": "Bashford", "given_name": "Luke", "orcid": "0000-0003-4391-2491", "clpid": "Bashford-L" }, { "family_name": "Kramer", "given_name": "Daniel", "orcid": "0000-0003-4551-2977", "clpid": "Kramer-D-R" }, { "family_name": "Lee", "given_name": "Brian", "clpid": "Lee-Brian" }, { "family_name": "Liu", "given_name": "Charles", "clpid": "Liu-Charles-Y" }, { "family_name": "Andersen", "given_name": "Richard A.", "orcid": "0000-0002-7947-0472", "clpid": "Andersen-R-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "We present a new deep multi-state Dynamic Recurrent Neural Network (DRNN) architecture for Brain Machine Interface (BMI) applications. Our DRNN is used to predict Cartesian representation of a computer cursor movement kinematics from open-loop neural data recorded from the posterior parietal cortex (PPC) of a human subject in a BMI system. We design the algorithm to achieve a reasonable trade-off between performance and robustness, and we constrain memory usage in favor of future hardware implementation. We feed the predictions of the network back to the input to improve prediction performance and robustness. We apply a scheduled sampling approach to the model in order to solve a statistical distribution mismatch between the ground truth and predictions. Additionally, we configure a small DRNN to operate with a short history of input, reducing the required buffering of input data and number of memory accesses. This configuration lowers the expected power consumption in a neural network accelerator. Operating on wavelet-based neural features, we show that the average performance of DRNN surpasses other state-of-the-art methods in the literature on both single- and multi-day data recorded over 43 days. Results show that multi-state DRNN has the potential to model the nonlinear relationships between the neural data and kinematics for robust BMIs.", "doi": "10.1101/710327", "publisher": "Neural Information Processing Systems Foundation, Inc.", "publication_date": "2019-12" }, { "id": "authors:7sx1p-35w88", "collection": "authors", "collection_id": "7sx1p-35w88", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190328-113108679", "type": "article", "title": "A 25-Gb/s Avalanche Photodetector-Based Burst-Mode Optical Receiver With 2.24-ns Reconfiguration Time in 28-nm CMOS", "author": [ { "family_name": "Chen", "given_name": "Kuan-Chang", "orcid": "0000-0003-2968-4656", "clpid": "Chen-Kuan-Chang" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper describes an avalanche photodetector (APD)-based optical receiver, applicable to the burst-mode operation, in 28-nm CMOS technology. With the aims of benefiting the overall optical link power efficiency and link bandwidth, the optical receiver is designed to have high sensitivity and high reconfiguration speed for burst-mode operation. The sensitivity of the receiver is optimized by adjusting the responsivity of APD via its reverse bias voltage, which leads to the highest signal-to-noise ratio (SNR) at the front end. The two-tap feed-forward equalization (FFE), along with two-tap decision feedback equalization, is implemented in a current-integrating fashion to further improve the sensitivity with superior power efficiency to their resistively loaded counterparts. Integrating dc comparator and integrating amplitude comparator are proposed to replace the conventional RC low-pass filters and peak detectors, respectively, in extracting the information of dc offset and signal amplitude within two unit intervals (UIs), empowering significant acceleration of the burst-mode reconfiguration. When the APD is biased at \u221216 V, its overall responsivity at 1310 nm is 4 A/W, and the optical receiver achieves bit-error-rate (BER) better than 10^(\u221212) at \u221216-dBm optical modulation amplitude, 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s.", "doi": "10.1109/JSSC.2019.2902471", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2019-06", "series_number": "6", "volume": "54", "issue": "6", "pages": "1682-1693" }, { "id": "authors:v5zew-cy026", "collection": "authors", "collection_id": "v5zew-cy026", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190814-153010702", "type": "book_section", "title": "High-speed optical links", "book_title": "2019 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Chen", "given_name": "Kuan-Chang", "orcid": "0000-0003-2968-4656", "clpid": "Chen-Kuan-Chang" }, { "family_name": "Hashemi", "given_name": "Arian", "clpid": "Hashemi-Arian" } ], "abstract": "This article consists only of a collection of slides from the author's conference presentation.", "doi": "10.1109/CICC.2019.8780245", "isbn": "978-1-5386-9395-7", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2019-04", "pages": "1-103" }, { "id": "authors:est3h-bh929", "collection": "authors", "collection_id": "est3h-bh929", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190523-133828806", "type": "book_section", "title": "Decoding Kinematics from Human Parietal Cortex using Neural Networks", "book_title": "2019 9th International IEEE/EMBS Conference on Neural Engineering (NER)", "author": [ { "family_name": "Shah", "given_name": "Sahil", "clpid": "Shah-Sahil" }, { "family_name": "Haghi", "given_name": "Benyamin", "orcid": "0000-0002-4839-7647", "clpid": "Haghi-Benyamin-Allahgholizadeh" }, { "family_name": "Kellis", "given_name": "Spencer", "orcid": "0000-0002-5158-1058", "clpid": "Kellis-Spencer-S" }, { "family_name": "Bashford", "given_name": "Luke", "orcid": "0000-0003-4391-2491", "clpid": "Bashford-L" }, { "family_name": "Kramer", "given_name": "Daniel", "orcid": "0000-0003-4551-2977", "clpid": "Kramer-D-R" }, { "family_name": "Lee", "given_name": "Brian", "clpid": "Lee-Brian" }, { "family_name": "Liu", "given_name": "Charles", "clpid": "Liu-Charles-Y" }, { "family_name": "Andersen", "given_name": "Richard", "orcid": "0000-0002-7947-0472", "clpid": "Andersen-R-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Brain-machine interfaces have shown promising results in providing control over assistive devices for paralyzed patients. In this work we describe a BMI system using electrodes implanted in the parietal lobe of a tetraplegic subject. Neural data used for the decoding was recorded in five 3-minute blocks during the same session. Within each block, the subject uses motor imagery to control a cursor in a 2D center-out task. We compare performance for four different algorithms: Kalman filter, a two-layer Deep Neural Network (DNN), a Recurrent Neural Network (RNN) with SimpleRNN unit cell (SimpleRNN), and a RNN with Long-Short-Term Memory (LSTM) unit cell. The decoders achieved Pearson Correlation Coefficients (\u03c1) of 0.48, 0.39, 0.77 and 0.75, respectively, in the Y-coordinate, and 0.24, 0.20, 0.46 and 0.47, respectively, in the X-coordinate.", "doi": "10.1109/ner.2019.8717137", "isbn": "9781538679210", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2019-03", "pages": "1138-1141" }, { "id": "authors:qkhw3-00p28", "collection": "authors", "collection_id": "qkhw3-00p28", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20191025-124827181", "type": "book_section", "title": "Wireless Implantable Intraocular Pressure Sensor with Parylene-Oil-Encapsulation and Forward-Angled RF Coil", "book_title": "2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS)", "author": [ { "family_name": "Shapero", "given_name": "Aubrey", "clpid": "Shapero-A-M" }, { "family_name": "Agarwal", "given_name": "Abhinav", "clpid": "Agarwal-A" }, { "family_name": "Martinez", "given_name": "Juan Carlos", "clpid": "Martinez-J-C" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Humayun", "given_name": "Mark S.", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" }, { "family_name": "Tai", "given_name": "Yu-Chong", "orcid": "0000-0001-8529-106X", "clpid": "Tai-Yu-Chong" } ], "abstract": "This paper presents a wireless and implantable intraocular pressure (IOP) sensor with parylene-oil-encapsulation packaging using a novel folded PCB architecture accomplishing practical RF coupling for power and data in a rabbit. The sensor is operated with an air gap of 5 mm between the primary coil and the animal, coupling to an on-chip coil at an input power of 32 dBm at 915 MHz, and can also be operated when the eyelid covers the sensor. Additionally, two novel results for parylene-on-oil deposition in general are presented. First, we show that the thickness of the porous layer of parylene-C (PA-C) and parylene-HT (PA-HT) deposited on silicone oils have a logarithmic decrease in porous layer thickness (PLT) versus silicone oil molecular weight (MW) over a range of 2\u2013139 kDa. Second, we directly verify that parylene-oil-encapsulated pressure sensors retain sensitivity despite material buildup for the first time.", "doi": "10.1109/memsys.2019.8870787", "isbn": "9781728116105", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2019-01", "pages": "21-24" }, { "id": "authors:3tnvh-re515", "collection": "authors", "collection_id": "3tnvh-re515", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190109-161530924", "type": "article", "title": "Energy-Efficient Classification for Resource-Constrained Biomedical Applications", "author": [ { "family_name": "Shoaran", "given_name": "Mahsa", "orcid": "0000-0002-6426-4799", "clpid": "Shoaran-M" }, { "family_name": "Haghi", "given_name": "Benyamin Allahgholizadeh", "orcid": "0000-0002-4839-7647", "clpid": "Haghi-Benyamin-Allahgholizadeh" }, { "family_name": "Taghavi", "given_name": "Milad", "orcid": "0000-0002-5512-0603", "clpid": "Taghavi-M" }, { "family_name": "Farivar", "given_name": "Masoud", "clpid": "Farivar-M" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Biomedical applications often require classifiers that are both accurate and cheap to implement. Today, deep neural networks achieve the state-of-the-art accuracy in most learning tasks that involve large data sets of unstructured data. However, the application of deep learning techniques may not be beneficial in problems with limited training sets and computational resources, or under domain-specific test time constraints. Among other algorithms, ensembles of decision trees, particularly the gradient boosted models have recently been very successful in machine learning competitions. Here, we propose an efficient hardware architecture to implement gradient boosted trees in applications under stringent power, area, and delay constraints, such as medical devices. Specifically, we introduce the concepts of asynchronous tree operation and sequential feature extraction to achieve an unprecedented energy and area efficiency. The proposed architecture is evaluated in automated seizure detection for epilepsy, using 3074 h of intracranial EEG data from 26 patients with 393 seizures. Average F1 scores of 99.23% and 87.86% are achieved for random and block-wise splitting of data into train/test sets, respectively, with an average detection latency of 1.1 s. The proposed classifier is fabricated in a 65-nm TSMC process, consuming 41.2 nJ/class in a total area of 540\u00d71850 \u03bcm^2 . This design improves the state-of-the-art by 27\u00d7 reduction in energy-area-latency product. Moreover, the proposed gradient-boosting architecture offers the flexibility to accommodate variable tree counts specific to each patient, to trade the predictive accuracy with energy. This patient-specific and energy-quality scalable classifier holds great promise for low-power sensor data classification in biomedical applications.", "doi": "10.1109/JETCAS.2018.2844733", "issn": "2156-3357", "publisher": "IEEE", "publication": "IEEE Journal on Emerging and Selected Topics in Circuits and Systems", "publication_date": "2018-12", "series_number": "4", "volume": "8", "issue": "4", "pages": "693-707" }, { "id": "authors:yxhv5-tv029", "collection": "authors", "collection_id": "yxhv5-tv029", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20181127-074755997", "type": "article", "title": "MRI-Inspired High-Resolution Localization for Biomedical Applications: Artificial Nuclear Spins on a Chip", "author": [ { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" } ], "abstract": "Significant advances have been made recently toward technologies such as smart pills to image the gastrointestinal tract [1], distributed sensors to map the function of the brain [2], and microscale swimming robots to access organs through the bloodstream [3]. Such technologies promise new ways to diagnose and treat diseases of local pathology, including neurodegeneration, autoimmune disease, cancer, and atherosclerosis. In fact, wireless microscale devices that navigate the body to diagnose and treat disease are key elements of the future of medicine, addressing localized malfunction in neurological, cardiovascular, autoimmune, cancer, and other disease areas.", "doi": "10.1109/MSSC.2018.2867406", "issn": "1943-0582", "publisher": "IEEE", "publication": "IEEE Solid-State Circuits Magazine", "publication_date": "2018-09", "series_number": "4", "volume": "10", "issue": "4", "pages": "34-42" }, { "id": "authors:1mnx1-d0p02", "collection": "authors", "collection_id": "1mnx1-d0p02", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20180926-123802831", "type": "article", "title": "Precision Wireless Implantable Continuous Intraocular Pressure Sensors Utilizing Parylene-on-oil Encapsulation", "author": [ { "family_name": "Rodger", "given_name": "Damien C.", "orcid": "0000-0002-1583-5946", "clpid": "Rodger-D-C" }, { "family_name": "Shapero", "given_name": "Aubrey", "clpid": "Shapero-A-M" }, { "family_name": "Agarwal", "given_name": "Abhinav", "clpid": "Agarwal-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Humayun", "given_name": "Mark S.", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" }, { "family_name": "Tai", "given_name": "Yu-Chong", "orcid": "0000-0001-8529-106X", "clpid": "Tai-Yu-Chong" } ], "abstract": "Purpose : To demonstrate the precision of a first of its kind fully implantable continuous wireless pressure sensor that measures true intraocular pressure (IOP) and leverages commercially fabricated microelectromechanical (MEMS) components with embedded temperature compensation to ensure superb reliability.\nMethods : The continuous IOP sensor, with a form factor similar to an aqueous shunt, is designed to be implanted with the electronics in the superotemporal or inferotemporal subtenon's space with a flexible 23-gauge silicone tube permanently inserted into the anterior chamber or the pars plana. It consists of a parylene-on-oil packaged LPS25H MEMS barometer with temperature compensation (STMicroelectronics, Geneva, Switzerland), capacitors, and a custom designed integrated circuit, all assembled on a flexible polyimide substrate. Devices were tested on the benchtop. Ex vivo porcine eyes were vitrectomized, and the IOP sensor tube placed into the pars plana through one of the sclerotomies. The IOP was varied using the pressure setting on the vitrector, and resultant pressure readings from the sensor were analyzed.\nResults : Photographs of the fabricated device are shown in Fig. 1(a-b).1 In air, the wireless device has demonstrated 0.17 mmHg pressure sensitivity. Accelerated-lifetime saline soak testing of the packaged barometer itself has demonstrated stability for an extrapolated 20 months to date. A photograph of the ex vivo wireless porcine eye setup is shown in Fig. 1c. In addition to excellent precision during IOP sweeps, a step from 5 to 75 resulted in a 69.92 mmHg change as measured by the sensor (Fig. 2). A slow ramp down after changing the setting on the vitrector back to 5 mmHg is seen because the eye is essentially a closed system.\nConclusions : A breakthrough wireless IOP sensor has been realized utilizing a commercially fabricated barometer and a custom integrated circuit as its backbone. All testing to date, including ex vivo porcine data, demonstrates superior reliability and precision.", "issn": "0146-0404", "publisher": "Association for Research in Vision and Ophthalmology (ARVO)", "publication": "Investigative Ophthalmology and Visual Science", "publication_date": "2018-07", "series_number": "9", "volume": "59", "issue": "9", "pages": "Art. No. 1997" }, { "id": "authors:mxrqh-2f263", "collection": "authors", "collection_id": "mxrqh-2f263", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20181102-143405625", "type": "book_section", "title": "A 41.2 nJ/class, 32-Channel On-Chip Classifier for Epileptic Seizure Detection", "book_title": "2018 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)", "author": [ { "family_name": "Taghavi", "given_name": "Milad", "orcid": "0000-0002-5512-0603", "clpid": "Taghavi-M" }, { "family_name": "Haghi", "given_name": "Benyamin A.", "orcid": "0000-0002-4839-7647", "clpid": "Haghi-Benyamin-Allahgholizadeh" }, { "family_name": "Farivar", "given_name": "Masoud", "clpid": "Farivar-M" }, { "family_name": "Shoaran", "given_name": "Mahsa", "orcid": "0000-0002-6426-4799", "clpid": "Shoaran-M" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A 41.2 nJ/class, 32-channel, patient-specific onchip classification architecture for epileptic seizure detection is presented. The proposed system-on-chip (SoC) breaks the strict energy-area-delay trade-off by employing area and memoryefficient techniques. An ensemble of eight gradient-boosted decision trees, each with a fully programmable Feature Extraction Engine (FEE) and FIR filters are continuously processing the input channels. In a closed-loop architecture, the FEE reuses a single filter structure to execute the top-down flow of the decision tree. FIR filter coefficients are multiplexed from a shared memory. The 540 \u00d7 1850 \u03bcm 2 prototype with a 1kB register-type memory is fabricated in a TSMC 65nm CMOS process. The proposed on-chip classifier is verified on 2253 hours of intracranial EEG (iEEG) data from 20 patients including 361 seizures, and achieves specificity of 88.1% and sensitivity of 83.7%. Compared to the state-of-the-art, the proposed classifier achieves 27 \u00d7 improvement in Energy-AreaLatency product.", "doi": "10.1109/EMBC.2018.8513243", "isbn": "978-1-5386-3646-6", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2018-07", "pages": "3693-3696" }, { "id": "authors:ry95w-qez53", "collection": "authors", "collection_id": "ry95w-qez53", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20180920-111853534", "type": "book_section", "title": "Towards Adaptive Deep Brain Stimulation in Parkinson's Disease: Lfp-Based Feature Analysis and Classification", "book_title": "2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)", "author": [ { "family_name": "Wang", "given_name": "Taige", "orcid": "0000-0001-7227-915X", "clpid": "Wang-Taige" }, { "family_name": "Shoaran", "given_name": "Mahsa", "orcid": "0000-0002-6426-4799", "clpid": "Shoaran-M" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Deep Brain Stimulation (DBS) is an established therapy for advanced Parkinson's disease (PD). Recent studies have applied the closed-loop control (adaptive DBS or aDBS) using feedback from local field potential (LFP) signals. However, current aDBS practices focus on simple feedback like beta band power and thresholding, without optimized control or classification algorithms. In this work, we study the capacity of several classifiers including automatic shrinkage linear discriminant analysis (LDA) to predict motor impairment. We use 20 features extracted from both monopolar and bipolar LFPs in 12 PD patients. In our best setting, we achieve a median accuracy of 70.2%, sensitivity of 81.2% and prediction lead time of 0.1 s across patients. By including relevant features other than beta power, a 13.6% improvement in accuracy is achieved. Moreover, the Hjorth parameters and high-frequency oscillation (HFO) features perform best according to the Analysis of Variance (ANOVA) p-value and classifier weights. These results suggest a great potential to improve current aDBS system for PD, by implementing a classifier with multiple features.", "doi": "10.1109/ICASSP.2018.8462472", "isbn": "978-1-5386-4658-8", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2018-04", "pages": "2536-2540" }, { "id": "authors:r1xy3-cfd74", "collection": "authors", "collection_id": "r1xy3-cfd74", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20180518-135417850", "type": "book_section", "title": "A wireless, low-drift, implantable intraocular pressure sensor with parylene-on-oil encapsulation", "book_title": "2018 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Agarwal", "given_name": "Abhinav", "clpid": "Agarwal-A" }, { "family_name": "Shapero", "given_name": "Aubrey", "clpid": "Shapero-A-M" }, { "family_name": "Rodger", "given_name": "Damien", "orcid": "0000-0002-1583-5946", "clpid": "Rodger-D-C" }, { "family_name": "Humayun", "given_name": "Mark", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" }, { "family_name": "Tai", "given_name": "Yu-Chong", "orcid": "0000-0001-8529-106X", "clpid": "Tai-Yu-Chong" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a wireless, implantable continuous intraocular pressure (IOP) monitoring system that features a parylene-on-oil sensor encapsulation method for achieving long-term low-drift in vivo. The system is implanted in the superotemporal quadrant of the eye between the sclera and conjunctiva. It consists of a commercial pressure sensor (STMicroelectronics LPS25H) with digital readout, a 65nm CMOS chip that supports wireless power/data telemetry and the I2C serial communication interface with the pressure sensor. The chip and pressure sensor are assembled on a flexible polyimide PCB, and then the sensor is submerged in biocompatible silicone oil and coated with parylene in situ. The implant uses an on-chip integrated RF coil to receive power from near-field RF coupling at 915 MHz and transmit measurement bits via RF-backscattering to an external reader. A 2 mm \u00d7 1.2 mm chip is fabricated in TSMC 65nm CMOS process. The IOP implant achieves a pressure sensitivity of 0.17 mm Hg with a total power consumption of 9.7\u03bcW. We demonstrate pressure offset drift of less than 0.5 mmHg for more than 4 months over a temperature range of 27\u201338 \u00b0C. The implant successfully tracks induced IOP variations in a porcine eye ex vivo, validating the system functionality and surgical implantation.", "doi": "10.1109/CICC.2018.8357049", "isbn": "978-1-5386-2483-8", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2018-04", "pages": "1-4" }, { "id": "authors:p4rdw-42331", "collection": "authors", "collection_id": "p4rdw-42331", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20180518-134714748", "type": "book_section", "title": "A 25Gb/s APD-based burst-mode optical receiver with 2.24ns reconfiguration time in 28nm CMOS", "book_title": "2018 IEEE Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Chen", "given_name": "Kuan-Chang", "orcid": "0000-0003-2968-4656", "clpid": "Chen-Kuan-Chang" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper describes an avalanche photodetector (APD) based burst-mode optical receiver in 28nm CMOS with 1-tap feed forward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion to improve the sensitivity. Integrating DC comparator and integrating amplitude comparator are proposed to replace the conventional RC low-pass filters and peak detectors, respectively, to reduce the reconfiguration time for burst-mode operation. The receiver achieves \u221216dBm sensitivity, 2.24ns reconfiguration time with 5dB dynamic range, and 1.37 pJ/bit energy efficiency at 25Gb/s.", "doi": "10.1109/CICC.2018.8357074", "isbn": "978-1-5386-2483-8", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2018-04", "pages": "1-4" }, { "id": "authors:qw6z7-6kk35", "collection": "authors", "collection_id": "qw6z7-6kk35", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20170731-162137444", "type": "article", "title": "Localization of Microscale Devices In Vivo using Addressable Transmitters Operated as Magnetic Spins", "author": [ { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Lee-Gosselin", "given_name": "Audrey", "orcid": "0000-0002-2431-2741", "clpid": "Lee-Gosselin-A" }, { "family_name": "Shapiro", "given_name": "Mikhail G.", "orcid": "0000-0002-0291-4215", "clpid": "Shapiro-M-G" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "The function of miniature wireless medical devices, such as capsule endoscopes, biosensors and drug-delivery systems, depends critically on their location inside the body. However, existing electromagnetic, acoustic and imaging-based methods for localizing and communicating with such devices suffer from limitations arising from physical tissue properties or from the performance of the imaging modality. Here, we embody the principles of nuclear magnetic resonance in a silicon integrated-circuit approach for microscale device localization. Analogous to the behaviour of nuclear spins, the engineered miniaturized radio frequency transmitters encode their location in space by shifting their output frequency in proportion to the local magnetic field; applied field gradients thus allow each device to be located precisely from its signal's frequency. The devices are integrated in circuits smaller than 0.7 mm3 and manufactured through a standard complementary-metal-oxide-semiconductor process, and are capable of sub-millimetre localization in vitro and in vivo. The technology is inherently robust to tissue properties, scalable to multiple devices, and suitable for the development of microscale devices to monitor and treat disease.", "doi": "10.1038/s41551-017-0129-2", "issn": "2157-846X", "publisher": "Nature Publishing Group", "publication": "Nature Biomedical Engineering", "publication_date": "2017-09", "series_number": "9", "volume": "1", "issue": "9", "pages": "736-744" }, { "id": "authors:08rht-p0w04", "collection": "authors", "collection_id": "08rht-p0w04", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20170816-163154635", "type": "book_section", "title": "A 4\u03bcW, ADPLL-based implantable amperometric biosensor in 65nm CMOS", "book_title": "2017 Symposium on VLSI Circuits", "author": [ { "family_name": "Agarwal", "given_name": "Abhinav", "clpid": "Agarwal-A" }, { "family_name": "Gural", "given_name": "Albert", "clpid": "Gural-A" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Adalian", "given_name": "Dvin", "clpid": "Adalian-D" }, { "family_name": "Chen", "given_name": "Sampson", "clpid": "Chen-Sampson" }, { "family_name": "Scherer", "given_name": "Axel", "orcid": "0000-0002-2160-9064", "clpid": "Scherer-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a fully implantable, wirelessly powered subcutaneous amperometric biosensor. We propose a novel ultra-low power all-digital phase-locked loop (ADPLL) based potentiostat architecture for electrochemical sensing. The system is wirelessly powered by near-field RF coupling of an on-chip antenna to an external coil at 915 MHz. Bi-directional wireless telemetry supports data transmission from the sensor to the external reader (uplink) via backscattering, and reconfiguration of the sensor chip over the RF downlink. The 1.2\u00d71.2 mm2 prototype is fabricated in TSMC 65nm CMOS process. The potentiostat achieves a 100pA sensitivity over a full scale current range of 0\u2013350nA. The total power consumption of the system is 4\u03bcW.", "doi": "10.23919/VLSIC.2017.8008566", "isbn": "978-4-86348-614-0", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2017-06", "pages": "C108-C109" }, { "id": "authors:rmpgm-nv048", "collection": "authors", "collection_id": "rmpgm-nv048", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20170613-164800173", "type": "book_section", "title": "Optical Interconnects: Design and Analysis", "book_title": "Optical Fiber Communication Conference 2017", "author": [ { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper focuses on design challenges and solutions for realization of low-power high-speed electronics for optical interconnects. Design methodologies for high sensitivity receivers and optimized driver circuitries at the transmitter side are presented.", "doi": "10.1364/OFC.2017.W4I.1", "isbn": "978-1-943580-23-1", "publisher": "OSA", "place_of_publication": "Washington, DC", "publication_date": "2017-03", "pages": "paper W4I.1" }, { "id": "authors:qcb6v-jr521", "collection": "authors", "collection_id": "qcb6v-jr521", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20160802-083727303", "type": "article", "title": "A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16-32 Gb/s Optical Receiver in 28 nm FDSOI CMOS", "author": [ { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "We present a novel frequency tracking method that exploits the dynamics of injection locking in a quadrature ring oscillator to increase the effective locking range from 5% (7-7.4 GHz) to 90% (4-11 GHz). The quadrature phase error between I and Q phases of an injection locked ring oscillator is derived and shown to contain frequency error information, both inside and outside the locking range. This error is utilized to form a first-order frequency tracking quadrature locked loop (QLL). This loop generates accurate clock phases for a 4-channel parallel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains a constant energy-per-bit consumption across 16-32 Gb/s by adaptive body biasing in a 28 nm FDSOI technology.", "doi": "10.1109/JSSC.2016.2584643", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2016-10", "series_number": "10", "volume": "51", "issue": "10", "pages": "2446-2462" }, { "id": "authors:fhrv1-pnb90", "collection": "authors", "collection_id": "fhrv1-pnb90", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190206-091232126", "type": "article", "title": "Professor Mark Horowitz: A Remarkable Innovator, Researcher, and Teacher [Guest Editorial]", "author": [ { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Presents an introduction to the issue devoted to the work and contributions of Mark Horowitz.", "doi": "10.1109/MSSC.2016.2579342", "issn": "1943-0582", "publisher": "IEEE", "publication": "IEEE Solid-State Circuits Magazine", "publication_date": "2016-09-02", "series_number": "3", "volume": "8", "issue": "3", "pages": "13" }, { "id": "authors:at4yz-3z885", "collection": "authors", "collection_id": "at4yz-3z885", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20161020-133924609", "type": "book_section", "title": "Hardware-friendly seizure detection with a boosted ensemble of shallow decision trees", "book_title": "2016 IEEE 38th Annual International Conference of the Engineering in Medicine and Biology Society (EMBC)", "author": [ { "family_name": "Shoaran", "given_name": "Mahsa", "orcid": "0000-0002-6426-4799", "clpid": "Shoaran-M" }, { "family_name": "Farivar", "given_name": "Masoud", "clpid": "Farivar-M" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Efficient on-chip learning is becoming an essential element of implantable biomedical devices. Despite a substantial literature on automated seizure detection algorithms, hardware-friendly implementation of such techniques is not sufficiently addressed. In this paper, we propose to employ a gradientboosted ensemble of decision trees to achieve a reasonable trade-off between detection accuracy and implementation cost. Combined with the proposed feature extraction model, we show that these classifiers quickly become competitive with more complex learning models previously proposed for hardware implementation, with only a small number of low-depth (d < 4) \"shallow\" trees. The results are verified on more than 3460 hours of intracranial EEG data including 430 seizures from 27 patients with epilepsy.", "doi": "10.1109/EMBC.2016.7591074", "isbn": "978-1-4577-0220-4", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2016-08", "pages": "1826-1829" }, { "id": "authors:fx5yx-8eh64", "collection": "authors", "collection_id": "fx5yx-8eh64", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20160802-075548837", "type": "article", "title": "A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS", "author": [ { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper describes an ultralow-power VCSEL transmitter in 32 nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. Driving the VCSEL in this condition increases its inherent nonlinearity. Conventional pre-emphasis techniques cannot compensate for this effect because they have a linear response. To overcome this limitation, a nonlinear equalization scheme is proposed. A dynamic VCSEL modelling technique is used to generate the time-domain optical responses for \"one\" and \"zero\" bits. Based on the asymmetry of the two responses, the rising and falling edges are equalized separately. Additionally, instead of using fixed bit delays, the equalization delay is selected based on the bias current of the VCSEL. The efficiency of the proposed modelling and equalization technique is evaluated through simulations and measurements. The transmitter achieves energy efficiency of 0.77 pJ/b at 20 Gb/s and occupies 100 \u00b5m x 60 \u00b5m active silicon area.", "doi": "10.1109/JSSC.2016.2553040", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2016-07", "series_number": "8", "volume": "51", "issue": "8", "pages": "1734-1743" }, { "id": "authors:e41rw-p6h66", "collection": "authors", "collection_id": "e41rw-p6h66", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20160622-132148230", "type": "article", "title": "A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Menezo", "given_name": "Sylvie", "clpid": "Menezo-S" }, { "family_name": "Pares", "given_name": "Gabriel", "clpid": "Pares-G" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Integrating optical receivers based on double-sampling architecture exhibit a low-power alternative to those designed around transimpedance amplifiers (TIA). In this paper, we present a 3D-integrated CMOS/silicon-photonic optical receiver. The receiver features a low-bandwidth TIA integrating front-end double-sampling technique and dynamic offset modulation. The copper-pillar-based 3D-integration technology used here enables ultralow parasitics and 40 \u03bcm pitch for interconnection. We study different tradeoffs in designing an optical receiver and how to choose between a full-bandwidth TIA front-end and integrating architecture using a resistive front-end or a low-bandwidth TIA front-end. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves \u221214.9 dBm of sensitivity and energy efficiency of 170 fJ/b at 25 Gb/s, while the conventional receiver achieves a sensitivity of \u221210.4 dBm and energy efficiency of 260 fJ/b at 21.2 Gb/s.", "doi": "10.1109/JLT.2015.2494060", "issn": "0733-8724", "publisher": "IEEE", "publication": "Journal of Lightwave Technology", "publication_date": "2016-06-15", "series_number": "12", "volume": "34", "issue": "12", "pages": "2924-2933" }, { "id": "authors:ac5v6-2c057", "collection": "authors", "collection_id": "ac5v6-2c057", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20161004-110833478", "type": "book_section", "title": "A 16-channel 1.1mm^2 implantable seizure control SoC with sub-\u03bcW/channel consumption and closed-loop stimulation in 0.18\u00b5m CMOS", "book_title": "VLSI Circuits Digest of Technical Papers, 2016 Symposium", "author": [ { "family_name": "Shoaran", "given_name": "Mahsa", "orcid": "0000-0002-6426-4799", "clpid": "Shoaran-M" }, { "family_name": "Shahshahani", "given_name": "Masoud", "clpid": "Shahshahani-M" }, { "family_name": "Farivar", "given_name": "Masoud", "clpid": "Farivar-M" }, { "family_name": "Almajano", "given_name": "Joyel", "clpid": "Almajano-J" }, { "family_name": "Shahshahani", "given_name": "Amirhossein", "clpid": "Shahshahani-A" }, { "family_name": "Schmid", "given_name": "Alexandre", "clpid": "Schmid-A" }, { "family_name": "Bragin", "given_name": "Anatol", "clpid": "Bragin-A" }, { "family_name": "Leblebici", "given_name": "Yusuf", "clpid": "Leblebici-Yusuf" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "We present a 16-channel seizure detection system-on-chip (SoC) with 0.92\u00b5W/channel power dissipation in a total area of 1.1mm^2 including a closed-loop neural stimulator. A set of four features are extracted from the spatially filtered neural data to achieve a high detection accuracy at minimal hardware cost. The performance is demonstrated by early detection and termination of kainic acid-induced seizures in freely moving rats and by offline evaluation on human intracranial EEG (iEEG) data. Our design improves upon previous works by over 40\u00d7 reduction in power-area product per channel. This improvement is a key step towards integration of larger arrays with higher spatiotemporal resolution to further boost the detection accuracy.", "doi": "10.1109/VLSIC.2016.7573557", "isbn": "978-1-5090-0634-2", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2016-06", "pages": "1-2" }, { "id": "authors:4adv5-2av65", "collection": "authors", "collection_id": "4adv5-2av65", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20161004-140125731", "type": "book_section", "title": "A 10Gb/s, 342fJ/bit Micro-Ring Modulator Transmitter with Switched-Capacitor Pre-Emphasis and Monolithic Temperature Sensor in 65nm CMOS", "book_title": "VLSI Circuits Digest of Technical Papers, 2016 Symposium", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "In this work, a CMOS-SiPh optical transmitter based on carrier-injection ring modulators is presented. It features a novel low-power switched-capacitor-based pre-emphasis that effectively compensates the modulator bandwidth limitation. A wavelength stabilization technique via direct measurement of ring temperature using a monolithic PTAT sensor is also presented. The optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit consumes 0.29mW.", "doi": "10.1109/VLSIC.2016.7573541", "isbn": "978-1-5090-0636-6", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2016-06", "pages": "1-2" }, { "id": "authors:w4c63-a9111", "collection": "authors", "collection_id": "w4c63-a9111", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20151216-111842883", "type": "book_section", "title": "Silicon-photonic PTAT Temperature Sensor for Micro-ring Resonator Thermal Stabilization", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents thermal stabilization of micro-ring resonator modulators through direct\nmeasurement of ring temperature using a monolithic PTAT temperature sensor. The measured\ntemperature is used in a feedback loop to adjust the thermal tuner of the ring.", "doi": "10.1109/ECOC.2015.7341733", "publisher": "IEEE", "publication_date": "2015-10" }, { "id": "authors:qn6nw-7h674", "collection": "authors", "collection_id": "qn6nw-7h674", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20151216-105345451", "type": "book_section", "title": "Differential Optical Ring Modulator: Breaking the Bandwidth/Quality-factor Trade-off", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Abiri", "given_name": "Behrooz", "orcid": "0000-0002-3317-2752", "clpid": "Abiri-B" }, { "family_name": "Hajimiri", "given_name": "Ali", "orcid": "0000-0001-6736-8019", "clpid": "Hajimiri-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "We present a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop.", "doi": "10.1109/ECOC.2015.7341731", "publisher": "IEEE", "publication_date": "2015-10" }, { "id": "authors:j9wry-jsz16", "collection": "authors", "collection_id": "j9wry-jsz16", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20151202-093844631", "type": "book_section", "title": "A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS", "author": [ { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper describes an ultra-low-power VCSEL transmitter in 32nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. The resulting nonlinearity and loss in bandwidth is modelled and compensated by a nonlinear equalization technique. The time domain optical responses for \"one\" and \"zero\" bits are used to find the optimum equalization technique. The rising and falling edges were equalized separately and the equalization delay is selected based on the bias current of the VCSEL. The transmitter achieves energy efficiency of 0.77pJ/b at 20Gb/s.", "doi": "10.1109/CICC.2015.7338415", "publisher": "IEEE", "publication_date": "2015-09" }, { "id": "authors:ng60v-y8x30", "collection": "authors", "collection_id": "ng60v-y8x30", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20151030-124526798", "type": "article", "title": "Silicon-photonic PTAT temperature sensor for micro-ring resonator thermal stabilization", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "We present a scheme for thermal stabilization of micro-ring resonator modulators through direct measurement of ring temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. The closed-loop feedback system is demonstrated to operate in presence of thermal perturbations at 20Gb/s.", "doi": "10.1364/OE.23.021875", "issn": "1094-4087", "publisher": "Optical Society of America", "publication": "Optics Express", "publication_date": "2015-08-24", "series_number": "17", "volume": "23", "issue": "17", "pages": "21875-21883" }, { "id": "authors:kdbp1-8kk59", "collection": "authors", "collection_id": "kdbp1-8kk59", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150824-123611696", "type": "article", "title": "An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a low-power first-order frequency synthesizer architecture suitable for high-speed on-chip clock generation. The proposed design features an architecture combining an LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, a phase interpolator, digital coarse-tuning and rotational frequency detection for fine-tuning. Similar to multiplying delay-locked loops (MDLLs), this architecture limits jitter accumulation to one reference cycle, as jitter during one reference cycle does not contribute to the next reference cycles. Also, instead of using multiplexer switches commonly employed in MDLLs, the reference clock edge is injected by phase interpolation to support higher frequencies and lower jitter. Functionality of the frequency synthesizer is validated between 8-9.5 GHz, LC VCO's range of operation. First-order dynamic of the acquisition has been analyzed and demonstrated through measurement. The output clock at 8 GHz has an integrated rms jitter of 490 fs, peak-to-peak periodic jitter of 2.06 ps and total rms jitter of 680 fs. Different components of jitter have been analyzed and separate measurements have been done to support the analysis. The reference spurs are measured to be -64.3 dB below the carrier frequency. At 8 GHz the system consumes 2.49 mW from a 1 V supply.", "doi": "10.1109/JSSC.2015.2424984", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2015-08", "series_number": "8", "volume": "50", "issue": "8", "pages": "1848-1860" }, { "id": "authors:6dfby-68s64", "collection": "authors", "collection_id": "6dfby-68s64", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150602-152044505", "type": "article", "title": "Capacitive Proximity Communication With Distributed Alignment Sensing for Origami Biomedical Implants", "author": [ { "family_name": "Loh", "given_name": "Matthew", "clpid": "Loh-M" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Origami implant design is a 3D integration technique which addresses size and cost constraints in biomedical implants. This paper presents a capacitive proximity interconnect scheme that enables chip-to-chip communication across folds in the Origami implant, allowing increased flexibility of chip placement and orientation. The capacitive plate array senses link quality and chip-to-chip alignment, and adapts the data rate at each plate accordingly, shutting down poorly-coupled links to save power. Instead of using separate plate arrays for alignment sensing and communication, this interconnect embeds the alignment sensor and transceiver arrays within the same set of plates, so that link quality can be measured at the communications plates directly, thus simplifying their adaptation to alignment. In order to save power and area, the sensor circuitry is distributed across the array and shares functional blocks with the transceiver. Data rates from 10-60 Mbps are achieved over 4-12 \u03bcm of parylene-C, with efficiencies up to 0.180 pJ/bit.", "doi": "10.1109/JSSC.2015.2404335", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2015-05", "series_number": "5", "volume": "50", "issue": "5", "pages": "1275-1286" }, { "id": "authors:jemq6-30j57", "collection": "authors", "collection_id": "jemq6-30j57", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150603-064209417", "type": "book_section", "title": "A 25Gbps 3D-Integrated CMOS/Silicon Photonic Optical Receiver with -15dBm Sensitivity and 0.17pJ/bit Energy Efficiency", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Menezo", "given_name": "Sylvie", "clpid": "Menezo-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "With continuous demand for higher bandwidth chip-to-chip communication, signaling over wires\nhas become extremely challenging [1]. Optical signaling is an attractive alternative due to its\nsmall frequency-dependent loss and higher bandwidth. Recent advances in silicon photonic\ndevices and 3D integration [2] have enabled them to be a viable solution for dense chip-to-chip\ninterconnection. A key design metric for interconnects is the link power efficiency at a specific\ndistance. In a modulator-based optical link, power is dissipated not only in the electronic\ncircuitry, but also in the laser source. Improving the sensitivity of the receiver, which translates to\nlower laser power, can significantly reduce the power consumption of the link. In this work, a\nhighly sensitive receiver topology is presented that is suitable for ultra-low capacitance frontends.", "doi": "10.1109/OIC.2015.7115663", "publisher": "IEEE", "publication_date": "2015-04" }, { "id": "authors:4xdw3-vgx22", "collection": "authors", "collection_id": "4xdw3-vgx22", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150605-135556686", "type": "book_section", "title": "Simulation and measurement of transcranial near infrared light penetration", "book_title": "Optical Interactions with Tissue and Cells XXVI", "author": [ { "family_name": "Yue", "given_name": "Lan", "clpid": "Yue-Lan" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Ozgur", "given_name": "Mehmet H.", "clpid": "Ozgur-M-H" }, { "family_name": "Murphy", "given_name": "Kevin", "clpid": "Murphy-K" }, { "family_name": "Louie", "given_name": "Stan", "clpid": "Louie-S" }, { "family_name": "Miller", "given_name": "Carol A.", "clpid": "Miller-C-A" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Humayun", "given_name": "Mark S.", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" } ], "contributor": [ { "family_name": "Jansen", "given_name": "E. Duco" } ], "abstract": "We are studying the transmission of LED array-emitted near-infrared (NIR) light through human tissues. Herein, we simulated and measured transcranial NIR penetration in highly scattering human head tissues. Using finite element analysis, we simulated photon diffusion in a multilayered 3D human head model that consists of scalp, skull, cerebral spinal fluid, gray matter and white matter. The optical properties of each layer, namely scattering and absorption coefficient, correspond to the 850 nm NIR light. The geometry of the model is minimally modified from the IEEE standard and the multiple LED emitters in an array were evenly distributed on the scalp. Our results show that photon distribution produced by the array exhibits little variation at similar brain depth, suggesting that due to strong scattering effects of the tissues, discrete spatial arrangements of LED emitters in an array has the potential to create a quasi-radially symmetrical illumination field. Measurements on cadaveric human head tissues excised from occipital, parietal, frontal and temporal regions show that illumination with an 850 nm LED emitter rendered a photon flux that closely follows simulation results. In addition, prolonged illumination of LED emitted NIR showed minimal thermal effects on the brain.", "doi": "10.1117/12.2077019", "isbn": "978-1-62841-411-0", "publisher": "SPIE", "place_of_publication": "Bellingham, Washington", "publication_date": "2015-03-05", "pages": "Art. No. 93210S" }, { "id": "authors:s5mwf-x8w57", "collection": "authors", "collection_id": "s5mwf-x8w57", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150324-095801684", "type": "book_section", "title": "22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS", "author": [ { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Modern SoC systems impose stringent requirements on on-chip clock\ngeneration and distribution. Ring-oscillator (RO) based injection-locked (IL)\nclocking has been used in the past [1] to provide a low-power, low-area and\nlow-jitter solution. Ring-based injection-locked oscillators (ILO) can also be\nused to generate quadrature phases from a reference clock [2] without\nfrequency division, which is desirable for half-rate and quarter-rate CDR.\nHowever, ILO inherently has a small locking range [3] making it less suitable for\nwideband applications. In addition, drift in the free-running frequency due to PVT\nvariations may lead to poor jitter performance and locking failures [4]. Adding a\nPLL to an ILO provides frequency tracking. However, PLL-aided techniques have\nsecond-order characteristics that lead to jitter peaking. They also add design\ncomplexity and power consumption [5]. We present a frequency-tracking\nmethod that exploits the dynamics of IL in a quadrature RO to increase the\neffective locking range. This quadrature locked loop (QLL) is used to generate\naccurate clock phases for a 4-channel optical receiver using a forwarded clock\nat quarter-rate (Fig. 22.3.1). The QLL drives an ILO at each channel without any\nrepeaters for local quadrature clock generation. Each local ILO has deskew\ncapability for phase alignment. The receiver maintains per-bit energy\nconsumption across wide data-rates (16 to 32Gb/s) by adaptive body biasing\n(BB) in a 28nm FDSOI technology.", "doi": "10.1109/ISSCC.2015.7063097", "publisher": "IEEE", "publication_date": "2015-02" }, { "id": "authors:txkhw-v4x89", "collection": "authors", "collection_id": "txkhw-v4x89", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150109-083348155", "type": "book_section", "title": "Design considerations for high-density fully intraocular epiretinal prostheses", "book_title": "2014 IEEE Biomedical Circuits and Systems Conference (BioCAS)", "author": [ { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Retinal prostheses have successfully proven to be a viable treatment for advanced stages of retinal degenerative diseases such as retinitis pigmetosa. However, current implementations have critical limitations that affect their functionality and resolution. This paper reviews design challenges of the electronics considering the biology of the eye and discusses new approaches for future high-density fully intraocular prostheses. An origami retinal implant that has the potential to alleviate the size, power and cost constraints of such systems is proposed. Measured results of enabling technologies are also discussed.", "doi": "10.1109/BioCAS.2014.6981703", "isbn": "9781479923465", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2014-10" }, { "id": "authors:wnw5n-11h40", "collection": "authors", "collection_id": "wnw5n-11h40", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150108-123604833", "type": "book_section", "title": "Wireline Transceivers", "book_title": "2014 IEEE Proceedings of the Custom Integrated Circuits Conference (CICC)", "author": [ { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Tam", "given_name": "Kimo", "clpid": "Tam-K" } ], "abstract": "High-bandwidth wireline communication continues to be crucial for many electronic systems today. Numerous research efforts are dedicated to enhance speed, power efficiency, flexibility, and ease-of-use of these transceivers. This session includes some of the latest advances in this domain. The first transceiver paper employs a sub-sampling ring oscillator phase-locked loop (PLL) to obtain a large frequency range with low jitter performance. The PLL is one of the most important blocks in a high-speed I/O link that generates the clocks for the receiver and transmitter of the system. In this paper the transmitter achieves 160fs RMS jitter and 10.9ps total jitter at 15.625 Gbps.", "doi": "10.1109/CICC.2014.6946110", "isbn": "9781479932870", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2014-09" }, { "id": "authors:kmzy7-2pc80", "collection": "authors", "collection_id": "kmzy7-2pc80", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20150310-075028459", "type": "book_section", "title": "An 8GHz First-order Frequency Synthesizer based on Phase\n Interpolation and Quadrature Frequency Detection in 65nm CMOS", "book_title": "2014 IEEE Proceedings of the Custom Integrated Circuits Conference (CICC),", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A low-power high-speed frequency synthesizer in 65nm CMOS is presented. The design features a novel architecture combining an LC quadrature VCO, two sample-and-holds, a phase interpolator, digital coarse-tuning and a novel quadrature frequency detection technique for fine-tuning. The system works based on injecting the rising edges of reference clock. The architecture has first-order dynamics, eliminating jitter accumulation. Functionality of the frequency synthesizer was validated between 8-9.5GHz, LC VCO's range of operation. The output clock at 8GHz has an integrated rms jitter of 0.5ps and peak-to-peak periodic jitter of 2.9ps. The reference spurs are -64.3dB below the carrier frequency. The system consumes 2.49mW from a 1V supply at 8GHz.", "doi": "10.1109/CICC.2014.6946021", "isbn": "978-1-4799-3286-3", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2014-09", "pages": "1-4" }, { "id": "authors:164wm-64g91", "collection": "authors", "collection_id": "164wm-64g91", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20151013-082613221", "type": "book_section", "title": "A 25Gb/s 170\u03bcW/Gb/s optical receiver in 28nm CMOS for chip-to-chip optical communication", "book_title": "2014 IEEE Radio Frequency Integrated Circuits Symposium", "author": [ { "family_name": "Saeedi", "given_name": "Saman", "clpid": "Saeedi-S" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receiver's sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design is compared with a conventional 3-stage TIA receiver via actual measurements. The proposed receiver architecture achieves error-free operation (BER<;10^(-12)) at 25Gb/s with energy efficiency of 170fJ/b while the conventional receiver achieves error-free operation at 17.1Gb/s with energy efficiency of 260fJ/b.", "doi": "10.1109/RFIC.2014.6851720", "isbn": "978-1-4799-3862-9", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2014-06", "pages": "283-286" }, { "id": "authors:4491m-fvz06", "collection": "authors", "collection_id": "4491m-fvz06", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140515-142406573", "type": "article", "title": "A Wideband Injection-Locking Scheme and Quadrature Phase Generation in 65-nm CMOS", "author": [ { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A novel technique for wideband injection locking in an LC oscillator is proposed. Phased-lock-loop and injection-locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter. This method does not require a phase frequency detector or a loop filter to achieve phase lock. A mathematical analysis of the system is presented and the expression for new locking range is derived. A locking range of 13.4-17.2 GHz and an average jitter tracking bandwidth of up to 400 MHz were measured in a high- Q LC oscillator. This architecture is used to generate quadrature phases from a single clock without any frequency division. It also provides high-frequency jitter filtering while retaining the low-frequency correlated jitter essential for forwarded clock receivers.", "doi": "10.1109/TMTT.2014.2310172", "issn": "0018-9480", "publisher": "IEEE", "publication": "IEEE Transactions on Microwave Theory and Techniques", "publication_date": "2014-04", "series_number": "4", "volume": "62", "issue": "4", "pages": "763-772" }, { "id": "authors:k5kgc-jwy54", "collection": "authors", "collection_id": "k5kgc-jwy54", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140225-114331568", "type": "article", "title": "A Fully Intraocular High-Density Self-Calibrating Epiretinal Prosthesis", "author": [ { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Chang", "given_name": "Han-Chieh", "clpid": "Chang-Han-Chieh" }, { "family_name": "Zhao", "given_name": "Yu", "clpid": "Zhao-Yu" }, { "family_name": "Weiland", "given_name": "James D.", "clpid": "Weiland-J-D" }, { "family_name": "Humayun", "given_name": "Mark S.", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" }, { "family_name": "Tai", "given_name": "Yu Chong", "orcid": "0000-0001-8529-106X", "clpid": "Tai-Yu-Chong" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a fully intraocular self-calibrating epiretinal prosthesis with 512 independent channels in 65 nm CMOS. A novel digital calibration technique matches the biphasic currents of each channel independently while the calibration circuitry is shared among every 4 channels. Dual-band telemetry for power and data with on-chip rectifier and clock recovery reduces the number of off-chip components. The rectifier utilizes unidirectional switches to prevent reverse conduction loss in the power transistors and achieves an efficiency > 80%. The data telemetry implements a phase-shift keying (PSK) modulation scheme and supports data rates up to 20 Mb/s. The system occupies an area of 4.5 \u00d73.1 mm^2. It features a pixel size of 0.0169 mm^2 and arbitrary waveform generation per channel. In vitro measurements performed on a Pt/Ir concentric bipolar electrode in phosphate buffered saline (PBS) are presented. A statistical measurement over 40 channels from 5 different chips shows a current mismatch with \u03bc = 1.12 \u03bcA and \u03c3 = 0.53 \u03bcA. The chip is integrated with flexible MEMS origami coils and parylene substrate to provide a fully intraocular implant.", "doi": "10.1109/TBCAS.2014.2298334", "issn": "1932-4545", "publisher": "IEEE", "publication": "IEEE Transactions on Biomedical Circuits and Systems", "publication_date": "2013-12", "series_number": "6", "volume": "7", "issue": "6", "pages": "747-760" }, { "id": "authors:xn1ts-5p046", "collection": "authors", "collection_id": "xn1ts-5p046", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140108-093848015", "type": "article", "title": "Introduction to the Special Issue on the 2013 IEEE\n International Solid-State Circuits Conference", "author": [ { "family_name": "Malcovati", "given_name": "Piero", "clpid": "Malcovati-P" }, { "family_name": "Brandt", "given_name": "Brian", "clpid": "Bandt-B" }, { "family_name": "Darabi", "given_name": "Hooman", "clpid": "Darabi-H" }, { "family_name": "Hashemi", "given_name": "Hossein", "clpid": "Hashemi-H" }, { "family_name": "Emami", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This Special Issue of the IEEE JOURNAL OF SOLID-STATE\nCIRCUITS is dedicated to the best papers taken from the\nAnalog, Data Converter, RF,Wireless, and Wireline Communications sessions at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, CA, USA, held in February 2013. As always, selecting a subset of papers from these high quality sessions proved to be a difficult task. However, we hope that the papers included in this issue are representative of the key innovations seen at the conference.", "doi": "10.1109/JSSC.2013.2278454", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2013-12", "series_number": "12", "volume": "48", "issue": "12", "pages": "2947-2951" }, { "id": "authors:vsqaz-hf123", "collection": "authors", "collection_id": "vsqaz-hf123", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190213-074612379", "type": "book_section", "title": "Capacitive proximity communication with distributed alignment sensing for origami biomedical implants", "book_title": "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference", "author": [ { "family_name": "Loh", "given_name": "Matthew", "clpid": "Loh-Matthew" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Origami implant design is a 3D integration technique which addresses size and cost constraints in biomedical implants. A capacitive proximity interconnect that enables this technique is presented. The interconnect embeds an alignment sensor that measures link quality directly and simplifies its adaptation to alignment. The sensor and transceiver share functional blocks, saving power and area. Data rates from 10-60 Mbps are achieved over 4-12 \u03bcm of parylene-C, with efficiencies up to 0.180 pJ/bit.", "doi": "10.1109/CICC.2013.6658445", "isbn": "978-1-4673-6146-0", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2013-09", "pages": "1-4" }, { "id": "authors:bjxsf-t7z56", "collection": "authors", "collection_id": "bjxsf-t7z56", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190213-082312832", "type": "book_section", "title": "A Wideband Injection-Locking Scheme and Quadrature Phase Generation in 65-nm CMOS", "book_title": "2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)", "author": [ { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A novel technique for wideband injection locking in an LC oscillator is proposed. PLL and injection locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter. This method doesn't require a phase frequency detector or a loop filter to achieve phase lock. 13.4GHz - 17.2GHz locking range and an average jitter tracking bandwidth of up to 400 MHz was measured in a high-Q LC oscillator. This architecture is used to generate quadrature phases form a single clock without any frequency division, and to provide high frequency jitter filtering while retaining the low frequency correlated jitter essential for clock forwarded receivers.", "doi": "10.1109/RFIC.2013.6569577", "isbn": "978-1-4673-6062-3", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2013-06", "pages": "261-264" }, { "id": "authors:8y0x7-6yv08", "collection": "authors", "collection_id": "8y0x7-6yv08", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20190213-083456432", "type": "book_section", "title": "A 20Gb/s 136fJ/b 12.5Gb/s/\u03bcm on-chip link in 28nm CMOS", "author": [ { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/\u03bcm) with BER<; 10^(-12). It has better than 136fJ/b of power efficiency at 10Gb/s. The total area of the transmitter and receiver is 1110\u03bcm^2.", "doi": "10.1109/RFIC.2013.6569576", "publisher": "IEEE", "publication_date": "2013-06" }, { "id": "authors:emdt5-kcg02", "collection": "authors", "collection_id": "emdt5-kcg02", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140520-140334969", "type": "book_section", "title": "Parylene origami structure for intraocular implantation", "book_title": "2013 Transducers & Eurosensors XXVII", "author": [ { "family_name": "Liu", "given_name": "Yang", "orcid": "0000-0002-8155-9134", "clpid": "Liu-Yang" }, { "family_name": "Park", "given_name": "Jungwook", "clpid": "Park-Jungwook" }, { "family_name": "Lang", "given_name": "Robert J.", "clpid": "Lang-R-J" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Pellegrino", "given_name": "Sergio", "orcid": "0000-0001-9373-3278", "clpid": "Pellegrino-S" }, { "family_name": "Humayun", "given_name": "Mark S.", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" }, { "family_name": "Tai", "given_name": "Yu-Chong", "orcid": "0000-0001-8529-106X", "clpid": "Tai-Yu-Chong" } ], "abstract": "This paper presents the use of origami technique to construct a 3D spherical structure from a 2D parylene-C (PA-C) film with designed folding crease patterns. This origami technique is developed or intended for intraocular epiretinal implant application, which requires a \"curved\" electrode array to match the curvature of the macula. The folding method and process are described here using silicone oil as a temporary glue to hold the folded structures through meniscus force. The temporary origami is then thermally set into permanent 3D shapes at 100 \u00b0C for 30 minutes in vacuum utilizing parylene-C's viscoelastic properties. The reported origami technique enables the possibility of first making an extended device in 2D format and, after a possible minimal surgical cut and insertion, then folding it into a 3D device inside the eye for necessary geometric matching with host tissues.", "doi": "10.1109/Transducers.2013.6627077", "isbn": "9781467359818", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2013-06", "pages": "1549-1552" }, { "id": "authors:5jjxp-hbj47", "collection": "authors", "collection_id": "5jjxp-hbj47", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20130401-143245883", "type": "article", "title": "A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication", "author": [ { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm CMOS technology. High data rate is achieved using an RC double-sampling front-end and a novel dynamic offset-modulation technique. The low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in transimpedance-amplifier (TIA) receivers. In addition, the demultiplexed output of the receiver helps save power in the following digital blocks. The receiver functionality was validated by electrical and optical measurements. The receiver achieves up to 24 Gb/s data rate with better than 160-\u03bcA current sensitivity in an experiment performed by a photodiode current emulator embedded on-chip. Optical measurements performed by a 1550-nm wire-bonded photodiode show better than - 4.7-dBm optical sensitivity at 24 Gb/s. The receiver offers peak power efficiency of 0.36 pJ/b at 20 Gb/s from a 1.2-V supply and occupies less than 0.0028 mm^2 silicon area.", "doi": "10.1109/JSSC.2012.2227612", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2013-02", "series_number": "2", "volume": "48", "issue": "2", "pages": "344-357" }, { "id": "authors:ay50a-hpk89", "collection": "authors", "collection_id": "ay50a-hpk89", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20170125-164509091", "type": "book_section", "title": "A fully intraocular 0.0169 mm^2/pixel 512-channel self-calibrating epiretinal prosthesis in 65nm CMOS", "book_title": "2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers", "author": [ { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Raj", "given_name": "Mayank", "clpid": "Raj-M" }, { "family_name": "Honarvar-Nazari", "given_name": "Meisam", "clpid": "Honarvar-Nazari-M" }, { "family_name": "Chang", "given_name": "Han-Chieh", "clpid": "Chang-Han-Chieh" }, { "family_name": "Zhao", "given_name": "Yu", "clpid": "Zhao-Yu" }, { "family_name": "Weiland", "given_name": "James", "clpid": "Weiland-J-D" }, { "family_name": "Humayun", "given_name": "Mark", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" }, { "family_name": "Tai", "given_name": "Yu-Chong", "orcid": "0000-0001-8529-106X", "clpid": "Tai-Yu-Chong" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Since their conception and success in human trials, the flexibility and spatial resolution of retinal prostheses have been of major interest. Clinical studies have revealed that hundreds of channels are needed to restore functional visual perception, and more sophisticated waveforms present advantages over biphasic pulses. Initial designs targeted stimulation current levels up to 1mA to ensure functionality. For such designs, an output compliance of >10V was required, and HV technologies were used at the expense of area and power consumption. Human clinical trials have recently shown that implanted electrodes present a stimulus threshold as low as 50\u03bcA. In addition, advances in implant technology promise close placement of electrode array and retinal tissue, which can further decrease the required current. Thus, highly scaled LV technologies can provide alternative means to reduce area and power, and to support hundreds of flexible independent channels for fully intraocular implants. In this paper, a self-calibrating 512-channel epiretinal prosthesis in 65nm CMOS is presented. It features dual-band telemetry for power and data, clock recovery, a 2-step calibration technique to match biphasic stimulation currents, and an independent arbitrary output waveform per channel. The implant integrates coils (power and data), IC, external capacitors and electrode array using a biocompatible parylene substrate, providing a fully intraocular solution.", "doi": "10.1109/ISSCC.2013.6487742", "isbn": "978-1-4673-4516-3", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2013-02", "pages": "296-297" }, { "id": "authors:ymwfe-01248", "collection": "authors", "collection_id": "ymwfe-01248", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20130729-090047591", "type": "book_section", "title": "Packaging study for a 512-channel intraocular epiretinal implant", "book_title": "IEEE 26th International Conference on Micro Electro Mechanical Systems (MEMS)", "author": [ { "family_name": "Chang", "given_name": "Jay Han-Chieh", "clpid": "Chang-Jay-Han-Chieh" }, { "family_name": "Liu", "given_name": "Yang", "orcid": "0000-0002-8155-9134", "clpid": "Liu-Yang" }, { "family_name": "Kang", "given_name": "Dongyang", "clpid": "Kang-Dongyang" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Zhao", "given_name": "Yu", "clpid": "Zhao-Yu" }, { "family_name": "Yu", "given_name": "Chia-Chen", "clpid": "Yu-Chia-Chen" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Weiland", "given_name": "James", "clpid": "Weiland-J-D" }, { "family_name": "Humayun", "given_name": "Mark", "orcid": "0000-0002-5830-5208", "clpid": "Humayun-M-S" }, { "family_name": "Tai", "given_name": "Yu-Chong", "orcid": "0000-0001-8529-106X", "clpid": "Tai-Yu-Chong" } ], "abstract": "Much effort has been put into developing multi-channel retinal prosthetic devices. Currently, even the most advanced prostheses do not have enough channels to provide vision to a desirable level. In this paper, we present a system design and a packaging scheme for a 512-channel intraocular epiretinal implant. Both a wireless power coil (with high transfer efficiency) and a data coil are included for this intraocular system. Simulation of the interference between coils is investigated and the results show that the two coils can be put in a co-planar fashion using two notch filters to minimize interference. The complete package is demonstrated with a mechanical model with a parylene-C flexible circuit board, i.e., parylene flex, to show the placement of the IC chips, discrete components, and coils. It also shows the final folded device after surgical insertion into an eye to save space. The feasibility of the proposed structure has been successfully tested in vivo. Experimentally, the maximum allowable pulling force is measured by a dynamic mechanical analysis (DMA) machine to be 8N, which provides a large safety margin for surgery.", "doi": "10.1109/MEMSYS.2013.6474428", "isbn": "978-1-4673-5654-1", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2013-01", "pages": "1045-1048" }, { "id": "authors:xs3gj-1c102", "collection": "authors", "collection_id": "xs3gj-1c102", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20121116-132920248", "type": "article", "title": "A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation", "author": [ { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a low-power receiver with two-tap decision feedback equalization (DFE) and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI CMOS process. The receiver employs a half-rate speculative DFE architecture to allow for the use of low-power front-end circuitry and CMOS clock buffers. In the proposed architecture, a switched-capacitor sample-hold at the front-end is employed to perform DFE tap summation. This technique is generalized to implement n taps of equalization. The receiver compensates the effect of crosstalk without making a decision on the received aggressor signal. Due to the low-power nature of the switched-capacitor front-end, the crosstalk cancellation is possible with only 33 \u03bcW/Gbps/lane power overhead. The receiver was tested over channels with different levels of loss and coupling. The signaling rate with BER < 10^(-12) was significantly increased with the use of DFE and crosstalk cancellation scheme for highly coupled and lossy PCB traces. The DFE receiver equalizes 15-Gb/s data over a channel with more than 14-dB loss while consuming about 7.5 mW from a 1.2-V supply. At lower data rates it equalizes channels with over 21-dB loss.", "doi": "10.1109/JSSC.2012.2203870", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2012-10", "series_number": "10", "volume": "47", "issue": "10", "pages": "2420-2432" }, { "id": "authors:q1taq-gmw96", "collection": "authors", "collection_id": "q1taq-gmw96", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140609-105129507", "type": "article", "title": "A Nonuniform Sampler for Wideband Spectrally-Sparse Environments", "author": [ { "family_name": "Wakin", "given_name": "Michael", "clpid": "Wakin-M-B" }, { "family_name": "Becker", "given_name": "Stephen", "clpid": "Becker-S" }, { "family_name": "Nakamura", "given_name": "Eric", "clpid": "Nakamura-E" }, { "family_name": "Grant", "given_name": "Michael", "clpid": "Grant-M" }, { "family_name": "Sovero", "given_name": "Emilio", "clpid": "Sovero-E-A" }, { "family_name": "Ching", "given_name": "Daniel", "clpid": "Ching-D" }, { "family_name": "Yoo", "given_name": "Juhwan", "clpid": "Yoo-J" }, { "family_name": "Romberg", "given_name": "Justin", "clpid": "Romberg-J-K" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Cand\u00e8s", "given_name": "Emmanuel", "orcid": "0000-0001-9234-924X", "clpid": "Cand\u00e8s-E-J" } ], "abstract": "We present a wide bandwidth, compressed sensing\nbased nonuniform sampling (NUS) system with a custom\nsample-and-hold chip designed to take advantage of a low\naverage sampling rate. By sampling signals nonuniformly, the\naverage sample rate can be more than a magnitude lower than\nthe Nyquist rate, provided that these signals have a relatively low information content as measured by the sparsity of their spectrum. The hardware design combines a wideband Indium-Phosphide heterojunction bipolar transistor sample-and-hold with a commercial off-the-shelf analog-to-digital converter to digitize an 800 MHz to 2 GHz band (having 100 MHz of noncontiguous spectral content) at an average sample rate of 236 Ms/s. Signal reconstruction is performed via a nonlinear compressed sensing algorithm, and the challenges of developing an efficient implementation\nare discussed. The NUS system is a general purpose\ndigital receiver. As an example of its real signal capabilities, measured bit-error-rate data for a GSM channel is presented, and comparisons to a conventional wideband 4.4 Gs/s ADC are made.", "doi": "10.1109/JETCAS.2012.2214635", "issn": "2156-3357", "publisher": "IEEE", "publication": "IEEE Journal on Emerging and Selected Topics in Circuits and Systems", "publication_date": "2012-09", "series_number": "3", "volume": "2", "issue": "3", "pages": "516-529" }, { "id": "authors:1e4qj-9tk69", "collection": "authors", "collection_id": "1e4qj-9tk69", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20120925-144241305", "type": "article", "title": "A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition", "author": [ { "family_name": "Yoo", "given_name": "Juhwan", "clpid": "Yoo-Juhwan" }, { "family_name": "Turnes", "given_name": "Christopher", "clpid": "Turnes-C" }, { "family_name": "Nakamura", "given_name": "Eric B.", "clpid": "Nakamura-E-B" }, { "family_name": "Le", "given_name": "Chi K.", "clpid": "Le-Chi-K" }, { "family_name": "Becker", "given_name": "Stephen", "clpid": "Becker-S" }, { "family_name": "Sovero", "given_name": "Emilio A.", "clpid": "Sovero-E-A" }, { "family_name": "Wakin", "given_name": "Michael B.", "clpid": "Wakin-M-B" }, { "family_name": "Grant", "given_name": "Michael C.", "clpid": "Grant-M-C" }, { "family_name": "Romberg", "given_name": "Justin", "clpid": "Romberg-J-K" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Cand\u00e8s", "given_name": "Emmanuel", "orcid": "0000-0001-9234-924X", "clpid": "Cand\u00e8s-E-J" } ], "abstract": "In this paper we present a complete (hardware/ software) sub-Nyquist rate (\u00d7 13) wideband signal acquisition chain capable of acquiring radar pulse parameters in an instantaneous bandwidth spanning 100 MHz-2.5 GHz with the equivalent of 8 effective number of bits (ENOB) digitizing performance. The approach is based on the alternative sensing-paradigm of compressed sensing (CS). The hardware platform features a fully-integrated CS receiver architecture named the random-modulation preintegrator (RMPI) fabricated in Northrop Grumman's 450 nm InP HBT bipolar technology. The software back-end consists of a novel CS parameter recovery algorithm which extracts information about the signal without performing full time-domain signal reconstruction. This approach significantly reduces the computational overhead involved in retrieving desired information which demonstrates an avenue toward employing CS techniques in power-constrained real-time applications. The developed techniques are validated on CS samples physically measured by the fabricated RMPI and measurement results are presented. The parameter estimation algorithms are described in detail and a complete description of the physical hardware is given.", "doi": "10.1109/JETCAS.2012.2214634", "issn": "2156-3357", "publisher": "IEEE", "publication": "IEEE Journal on Emerging and Selected Topics in Circuits and Systems", "publication_date": "2012-09", "series_number": "3", "volume": "2", "issue": "3", "pages": "626-638" }, { "id": "authors:n1a1k-44b16", "collection": "authors", "collection_id": "n1a1k-44b16", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140820-153017399", "type": "book_section", "title": "A low-power 20Gb/s transmitter in 65nm CMOS technology", "book_title": "2012 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)", "author": [ { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A 20Gb/s transmitter employing an analog filtering pre-emphasis equalization technique is presented. The transmitter dissipates 10mW from a 1.2V supply and occupies 0.01mm2. This high-frequency boosting equalization technique allows for compensating channel losses up to 20dB at Nyquist-rate. The prototype was fabricated in 65nm CMOS technology and characterized using lossy cables and 5\" and 10\" FR4 PCB traces.", "doi": "10.1109/RFIC.2012.6242252", "isbn": "978-1-4673-0413-9", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2012-06", "pages": "149-152" }, { "id": "authors:xsj2r-pz295", "collection": "authors", "collection_id": "xsj2r-pz295", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140820-151805881", "type": "book_section", "title": "A 100MHz\u20132GHz 12.5x sub-Nyquist rate receiver in 90nm CMOS", "book_title": "2012 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)", "author": [ { "family_name": "Yoo", "given_name": "Juhwan", "clpid": "Yoo-Juhwan" }, { "family_name": "Becker", "given_name": "Stephen", "clpid": "Becker-S" }, { "family_name": "Loh", "given_name": "Matthew", "clpid": "Loh-Matthew" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Cand\u00e8s", "given_name": "Emmanuel", "orcid": "0000-0001-9234-924X", "clpid": "Cand\u00e8s-E-J" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A fully-integrated, high-speed, wideband receiver\ncalled the random modulation pre-integrator is realized in IBM 90nm digital CMOS. It achieves an effective instantaneous bandwidth of 2GHz, with >54dB dynamic range. Most notably, the aggregate digitization rate is \u0192_s =320MSPS, 12.5\u00d7 below the Nyquist rate. Signal recovery can be accomplished for any signal with a concise representation. The system is validated using radar-pulses and tones as the input and recovering the time-domain\nwaveforms.", "doi": "10.1109/RFIC.2012.6242225", "isbn": "978-1-4673-0413-9", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2012-06", "pages": "31-34" }, { "id": "authors:zm3ef-j2g53", "collection": "authors", "collection_id": "zm3ef-j2g53", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20120627-124652440", "type": "book_section", "title": "Ultra Low-Power Receiver Design for Dense Optical Interconnects", "book_title": "2012 IEEE Optical Interconnects Conference", "author": [ { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "With the increasing bandwidth requirements of computing systems and limitations on power consumption, optical\nsignaling for chip-to-chip interconnects has gained a lot of interest. Hybrid integration of optical devices with\nelectronics has been demonstrated to achieve high performance [1]-[4], and recent advances in silicon photonics have led to fully integrated systems [5]. These approaches pave the way to massively parallel optical\ncommunications. Dense arrays of optical detectors require very low-power, sensitive, and compact optical receiver\ncircuits. Existing designs for the input receiver, such as TIA, require large power consumption to achieve high\nbandwidth and low noise, and can occupy large area due to bandwidth enhancement inductors. In this work, a\ncompact low-power optical receiver that scales well with technology has been designed to explore the potential of\noptical signaling for future chip-to-chip and on-chip communication. In most optical receivers, the photodiode\ncurrent is converted to a voltage signal. A simple resistor can perform the I-V conversion if the resulting RC time\nconstant is in the order of the bit interval (T_b) [5]. However, for a given photodiode capacitance and target SNR, the\nRC limits the bandwidth and hence the data rate. To avoid this problem, TIAs are commonly employed, which are\nhighly analog, power hungry, and do not scale well with technology. One alternative is the integrating front-end to\neliminate the need for resistance and breaking the bandwidth trade-off. However, this technique suffers from voltage\nheadroom limitations, and requires short-length DC-balanced inputs [6]. The proposed receiver resolves this\nproblem by employing an integrating RC front-end along with dynamic offset modulation technique that decouple\nthe bandwidth/data-rate and integration/headroom trade-offs [7].", "doi": "10.1109/OIC.2012.6224419", "isbn": "978-1-4577-1620-1", "publisher": "IEEE", "publication_date": "2012-05", "pages": "115-116" }, { "id": "authors:w0gmw-fr543", "collection": "authors", "collection_id": "w0gmw-fr543", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20120907-092240681", "type": "book_section", "title": "An analog sub-linear time sparse signal acquisition framework based on structured matrices", "book_title": "2012 International Conference on Acoustics, Speech and Signal Processing", "author": [ { "family_name": "Yoo", "given_name": "Juhwan", "clpid": "Yoo-J" }, { "family_name": "Khajehnejad", "given_name": "Amin", "clpid": "Khajehnejad-A" }, { "family_name": "Hassibi", "given_name": "Babak", "orcid": "0000-0002-1375-5838", "clpid": "Hassibi-B" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Advances in compressed-sensing (CS) have sparked interest in designing information acquisition systems that process data at close to the information rate. Initial proposals for CS signal acquisition systems utilized random matrix ensembles in conjunction with convex relaxation based signal reconstruction algorithms. While providing universal performance bounds, random matrix based formulations present several practical problems due to: the difficulty in physically implementing key mathematical operations, and their dense representation. In this paper, we present a CS architecture which is based on a sub-linear time recovery algorithm (with minimum memory requirement) that exploits a novel structured matrix. This formulation allows the use of a reconstruction algorithm based on relatively simple computational primitives making it more amenable to implementation in a fully-integrated form. Theoretical recovery guarantees are discussed and a hypothetical physical CS decoder is described.", "doi": "10.1109/ICASSP.2012.6289122", "isbn": "978-1-4673-0045-2", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2012-03", "pages": "5321-5324" }, { "id": "authors:w6nby-tg884", "collection": "authors", "collection_id": "w6nby-tg884", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20120320-133331713", "type": "article", "title": "A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O", "author": [ { "family_name": "Loh", "given_name": "Matthew", "clpid": "Loh-M" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a novel all-digital CDR scheme in 90 nm CMOS. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data (\"data clock\") and the other is swept across the delay line (\"search clock\"). As the search clock is swept, its samples are compared against the data samples to generate eye information. This information is used to determine the best phase for data recovery. After placing the search clock at this phase, search and data functions are traded between clocks and eye monitoring repeats. By trading functions, infinite delay range is realized using only a calibrated delay line, instead of a PLL or DLL. Since each clock generates its own alignment information, mismatches in clock distribution can be tolerated. The scheme's generalized sampling and retiming architecture is used in an efficient sharing technique that reduces the number of clocks required, saving power and area in high-density interconnect. The shared CDR is implemented using static CMOS logic in a 90 nm bulk process, occupying 0.15 mm^2. It operates from 6 to 9 Gb/s, and consumes 2.5 mW/Gb/s of power at 6 Gb/s and 3.8 mW/Gb/s at 9 Gb/s.", "doi": "10.1109/JSSC.2011.2178557", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2012-03", "series_number": "3", "volume": "47", "issue": "3", "pages": "641-651" }, { "id": "authors:bg7tg-rww27", "collection": "authors", "collection_id": "bg7tg-rww27", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20120907-095250187", "type": "book_section", "title": "Design and implementation of a fully integrated compressed-sensing signal acquisition system", "book_title": "2012 International Conference on Acoustics, Speech and Signal Processing", "author": [ { "family_name": "Yoo", "given_name": "Juhwan", "clpid": "Yoo-Juhwan" }, { "family_name": "Becker", "given_name": "Stephen", "clpid": "Becker-S" }, { "family_name": "Monge", "given_name": "Manuel", "orcid": "0000-0001-9799-0693", "clpid": "Monge-Manuel" }, { "family_name": "Loh", "given_name": "Matthew", "clpid": "Loh-Matthew" }, { "family_name": "Cand\u00e8s", "given_name": "Emmanuel", "orcid": "0000-0001-9234-924X", "clpid": "Cand\u00e8s-E-J" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Compressed sensing (CS) is a topic of tremendous interest because it provides theoretical guarantees and computationally tractable algorithms to fully recover signals sampled at a rate close to its information content. This paper presents the design of the first physically realized fully-integrated CS based Analog-to-Information (A2I) pre-processor known as the Random-Modulation Pre-Integrator (RMPI) [1]. The RMPI achieves 2GHz bandwidth while digitizing samples at a rate 12.5\u00d7 lower than the Nyquist rate. The success of this implementation is due to a coherent theory/algorithm/hardware co-design approach. This paper addresses key aspects of the design, presents simulation and hardware measurements, and discusses limiting factors in performance.", "doi": "10.1109/ICASSP.2012.6289123", "isbn": "978-1-4673-0045-2", "publisher": "IEEE", "place_of_publication": "Piscataway NJ", "publication_date": "2012-03", "pages": "5325-5328" }, { "id": "authors:mndx8-c2120", "collection": "authors", "collection_id": "mndx8-c2120", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140820-151052084", "type": "book_section", "title": "An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication", "book_title": "2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)", "author": [ { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "Using optics for chip-to-chip interconnects has recently gained a lot of interest. As data rates scale to meet increasing bandwidth requirements, the shortcomings of copper channels are becoming more severe. Hybrid integration of optical devices with electronics has been demonstrated to achieve high performance, and recent advances in silicon photonics have led to fully integrated optical signaling. These approaches pave the way to massively parallel optical communications. Dense arrays of optical detectors require very low-power, sensitive, and compact optical receiver circuits. Existing designs for the input receiver, such as TIA, require large power consumption to achieve high band width and low noise, and can occupy large area due to bandwidth-enhancement inductors. In this work, a compact low-power optical receiver that scales well with technology is designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication.", "doi": "10.1109/ISSCC.2012.6176949", "isbn": "978-1-4673-0376-7", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2012-02", "pages": "130-131" }, { "id": "authors:88mdy-40z44", "collection": "authors", "collection_id": "88mdy-40z44", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140820-145943216", "type": "book_section", "title": "A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation", "book_title": "2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)", "author": [ { "family_name": "Nazari", "given_name": "Meisam Honarvar", "clpid": "Nazari-M-H" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "In this paper, we present a low-power receiver that supports high data rates over bandwidth-limited and coupled links. The receiver employs a half-rate 2-tap speculative DFE architecture with a far-end cross-talk (FEXT) cancellation technique. Figure 25.6.1 shows the top-level architecture of the DFE receiver. Conventionally, analog taps of the equalizer are implemented using current mode summers, thus the power consumption of the DFE increases proportion ally with the number of taps. In the proposed architecture, a switched-capacitor S/H is employed to sample the input signal and combine it with the feedback coefficients at the front-end of the receiver, as shown in Fig. 25.6.2 (S/H/summer). In this design, the switched-capacitor network is modified to support two taps of DFE without any signal loss. This technique can be further extended to realize more number of taps. The extra power due to sampling capacitors, switches and voltage-mode DACs is very small.", "doi": "10.1109/ISSCC.2011.5746391", "isbn": "978-1-61284-303-2", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2011-02", "pages": "446-448" }, { "id": "authors:qrsf2-47g11", "collection": "authors", "collection_id": "qrsf2-47g11", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20110329-081801877", "type": "book_section", "title": "All-Digital CDR for High-Density, High-Speed I/O", "book_title": "2010 Symposium on VLSI Circuits", "author": [ { "family_name": "Loh", "given_name": "Matthew", "clpid": "Loh-M" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "A novel all-digital CDR for source-synchronous links, and\nits implementation in 90nm CMOS, is presented. A phase\nalignment technique with ping-pong action between two\nclock phases is used. The system is implemented in static\nCMOS logic, occupies 0.234 mm^2 and dissipates 16.6 mW at\n6 Gb/s, demonstrating BER < 10^(-13) with PRBS-7 input. The\ncompactness and all-static-CMOS nature of the system make\nit suitable for use in high-speed I/Os requiring per-pin\nsynchronization.", "doi": "10.1109/VLSIC.2010.5560319", "isbn": "978-1-4244-7636-7", "publisher": "IEEE", "publication_date": "2010", "pages": "147-148" }, { "id": "authors:af6mr-tth43", "collection": "authors", "collection_id": "af6mr-tth43", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:PALieeejssc08", "type": "article", "title": "A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects", "author": [ { "family_name": "Palermo", "given_name": "Samuel", "clpid": "Palermo-S" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Horowitz", "given_name": "Mark", "clpid": "Horowitz-M" } ], "abstract": "Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2.", "doi": "10.1109/JSSC.2008.920330", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2008-05", "series_number": "5", "volume": "43", "issue": "5", "pages": "1235-1246" }, { "id": "authors:bx1bn-qe155", "collection": "authors", "collection_id": "bx1bn-qe155", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:20140609-103233137", "type": "book_section", "title": "Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology", "book_title": "IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007.", "author": [ { "family_name": "Agah", "given_name": "Amir", "clpid": "Agah-A" }, { "family_name": "Fakhraie", "given_name": "S. Mehdi", "clpid": "Fakhraie-S-M" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" } ], "abstract": "This paper presents a new 32-bit adder structure\nwith 12 GHz low-power operation in 65nm technology. The Fast\nConditional Sparse-Tree Logic (FCSL) is based on modifying the initial Sparse-Tree architecture [1] to enhance its speed using tertiary trees and applying a carry-select scheme in some of the more significant bits. This design has been compared with the Sparse-Tree adder and the Low-Voltage Swing adder in terms of speed and power. It has been shown that speed can be improved using FCSL architecture while keeping the power at a comparable level.", "doi": "10.1109/ISCAS.2007.377979", "isbn": "1-4244-0920-9", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2007-05", "pages": "3006-3009" }, { "id": "authors:v6kg6-69x77", "collection": "authors", "collection_id": "v6kg6-69x77", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:EMAieeejssc07", "type": "article", "title": "A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE", "author": [ { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Varzaghani", "given_name": "Aida", "clpid": "Varzaghani-A" }, { "family_name": "Bulchacchelli", "given_name": "John F.", "clpid": "Bulchacchelli-J-F" }, { "family_name": "Rylyakov", "given_name": "Alexander", "clpid": "Rylyakov-A" }, { "family_name": "Yang", "given_name": "Chih-Kong Ken", "clpid": "Yang-Chih-Kong-Ken" }, { "family_name": "Friedman", "given_name": "Daniel J.", "clpid": "Friedman-D-J" } ], "abstract": "A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally.", "doi": "10.1109/JSSC.2007.892156", "issn": "0018-9200", "publisher": "IEEE", "publication": "IEEE Journal of Solid-State Circuits", "publication_date": "2007-04", "series_number": "4", "volume": "42", "issue": "4", "pages": "889-896" }, { "id": "authors:47ey5-3f917", "collection": "authors", "collection_id": "47ey5-3f917", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:PALisscc07", "type": "book_section", "title": "A 90nm CMOS 16Gb/s transceiver for optical interconnects", "book_title": "IEEE International Solid-State Circuits Conference (ISSCC 2007), Digest of Technical Papers. San Francisco, CA", "author": [ { "family_name": "Palermo", "given_name": "Samuel", "clpid": "Palermo-S" }, { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Horowitz", "given_name": "Mark", "clpid": "Horowitz-M" } ], "abstract": "An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and an integrating/double-sampling RX to eliminate the need for a bit-rate TIA. A dual-loop CDR with baud-rate phase detection further reduces power and area. Fabricated in a 1V 90nm CMOS process, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm^2.", "doi": "10.1109/ISSCC.2007.373579", "isbn": "1424408539", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2007-02", "pages": "44-45, 586" }, { "id": "authors:7nsgk-nbn49", "collection": "authors", "collection_id": "7nsgk-nbn49", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic06", "type": "book_section", "title": "A low-power receiver with switched-capacitor summation DFE", "book_title": "Symposium on VLSI Circuits, 2006. Digest of Technical Papers", "author": [ { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Varzaghani", "given_name": "Aida", "clpid": "Varzaghani-A" }, { "family_name": "Bulzacchelli", "given_name": "John", "clpid": "Bulzacchelli-J" }, { "family_name": "Rylyakov", "given_name": "Alexander", "clpid": "Rylyakov-A" }, { "family_name": "Yang", "given_name": "Chih-Kong Ken", "clpid": "Yang-Chih-Kong-Ken" }, { "family_name": "Friedman", "given_name": "Daniel", "clpid": "Friedman-D" } ], "abstract": "A low power receiver with a one tap DFE was fabricated in 90mm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply.", "doi": "10.1109/VLSIC.2006.1705375", "isbn": "1-4244-0006-6", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2006-06", "pages": "192-193" }, { "id": "authors:7n4zx-cn560", "collection": "authors", "collection_id": "7n4zx-cn560", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:MILisscc05", "type": "book_section", "title": "Opportunities for optics in integrated circuits applications", "book_title": "IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC '05, San Francisco", "author": [ { "family_name": "Miller", "given_name": "D. A. B.", "clpid": "Miller-D-A-B" }, { "family_name": "Bhatnagar", "given_name": "A.", "clpid": "Bhatnagar-A" }, { "family_name": "Palermo", "given_name": "S.", "clpid": "Palermo-S" }, { "family_name": "Emami-Neyestanak", "given_name": "A.", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Horowitz", "given_name": "M. A.", "clpid": "Horowitz-M-A" } ], "abstract": "Optics potentially addresses two key problems in electronic chips and systems: interconnects and timing. Short optical pulses (e.g., picoseconds or shorter) offer particularly precise timing. Results are shown for optical and electrical four-phase clocking, with <1 ps rms jitter for the optical case.", "doi": "10.1109/ISSCC.2005.1493881", "isbn": "0780389042", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2005-02", "pages": "86-87" }, { "id": "authors:d9cgx-dt943", "collection": "authors", "collection_id": "d9cgx-dt943", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic04", "type": "book_section", "title": "CMOS transceiver with baud rate clock recovery for optical interconnects", "book_title": "Symposium on VLSI Circuits, 2004. Digest of Technical Papers.", "author": [ { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Palermo", "given_name": "Samuel", "clpid": "Palermo-S" }, { "family_name": "Lee", "given_name": "Hae-Chang", "clpid": "Lee-Hae-Chang" }, { "family_name": "Horowitz", "given_name": "Mark", "clpid": "Horowitz-M" } ], "abstract": "An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 \u03bcm CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.", "isbn": "0-7803-8287-0", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2004-06", "pages": "410-413" }, { "id": "authors:9smce-ttg69", "collection": "authors", "collection_id": "9smce-ttg69", "cite_using_url": "https://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic02", "type": "book_section", "title": "A 1.6 Gb/s, 3 mW CMOS receiver for optical communication", "book_title": "Symposium on VLSI Circuits, Digest of Technical Papers, 2002.", "author": [ { "family_name": "Emami-Neyestanak", "given_name": "Azita", "orcid": "0000-0002-6945-9958", "clpid": "Emami-A" }, { "family_name": "Liu", "given_name": "Dean", "clpid": "Liu-Dean" }, { "family_name": "Keeler", "given_name": "Gordon", "clpid": "Keeler-G" }, { "family_name": "Helman", "given_name": "Noah", "clpid": "Helman-N" }, { "family_name": "Horowitz", "given_name": "Mark", "clpid": "Horowitz-M" } ], "abstract": "A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-\u03bcm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially \"AC couples\" the input. The resulting receiver resolves an 11 \u03bcA input, dissipates 3 mW of power, occupies 80 \u03bcm x 50 \u03bcm of area and operates at over 1.6 Gb/s.", "doi": "10.1109/VLSIC.2002.1015053", "isbn": "0-7803-7310-3", "publisher": "IEEE", "place_of_publication": "Piscataway, NJ", "publication_date": "2002-06", "pages": "84-87" } ]