<h1>DeHon, Andre</h1>
<h2>Book Chapter from <a href="https://data.caltech.edu">CaltechTHESIS committee</a></h2>
<ul>
<li>DeLorimier, Michael John (2013) <a href="https://resolver.caltech.edu/CaltechTHESIS:08192012-145253489">GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms</a>; <a href="https://doi.org/10.7907/M3TW-7Y53">10.7907/M3TW-7Y53</a></li>
<li>Mehta, Nikil (2013) <a href="https://resolver.caltech.edu/CaltechTHESIS:10072012-230900231">An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping</a>; <a href="https://doi.org/10.7907/358S-CW22">10.7907/358S-CW22</a></li>
<li>Kapre, Nachiket Ganesh (2011) <a href="https://resolver.caltech.edu/CaltechTHESIS:10262010-082537998">SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator
</a>; <a href="https://doi.org/10.7907/QVZR-VB52">10.7907/QVZR-VB52</a></li>
<li>Naeimi, Helia (2008) <a href="https://resolver.caltech.edu/CaltechETD:etd-01242008-012650">Reliable Integration of Terascale Systems with Nanoscale Devices</a>; <a href="https://doi.org/10.7907/P842-7B49">10.7907/P842-7B49</a></li>
<li>Prakash, Piyush (2008) <a href="https://resolver.caltech.edu/CaltechETD:etd-05262008-234258">Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching</a>; <a href="https://doi.org/10.7907/9HMY-RR92">10.7907/9HMY-RR92</a></li>
<li>Papadantonakis, Karl Spyros (2006) <a href="https://resolver.caltech.edu/CaltechETD:etd-01132006-152609">Rigorous Analog Verification of Asynchronous Circuits</a>; <a href="https://doi.org/10.7907/4R8F-WF03">10.7907/4R8F-WF03</a></li>
<li>Wong, Catherine Grace (2004) <a href="https://resolver.caltech.edu/CaltechTHESIS:11192009-161338958">High-Level Synthesis and Rapid Prototyping of Asynchronous VLSI Systems</a>; <a href="https://doi.org/10.7907/5N2N-0W58">10.7907/5N2N-0W58</a></li>
<li>Pénzes, Paul Ivan (2002) <a href="https://resolver.caltech.edu/CaltechTHESIS:03022011-131111881">Energy-Delay Complexity of Asynchronous Circuits</a>; <a href="https://doi.org/10.7907/9jpj-5s67">10.7907/9jpj-5s67</a></li>
<li>Nyström, Mika (2001) <a href="https://resolver.caltech.edu/CaltechTHESIS:10152010-145548970">Asynchronous Pulse Logic</a>; <a href="https://doi.org/10.7907/B107-MW15">10.7907/B107-MW15</a></li>
<li>Fan, Chenggong Charles (2001) <a href="https://resolver.caltech.edu/CaltechETD:etd-08152001-144501">Fault-tolerant cluster of networking elements</a>; <a href="https://doi.org/10.7907/R15B-VD58">10.7907/R15B-VD58</a></li>
</ul>