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    title = "SPICEĀ²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator
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    year = "2011",
    url = "https://resolver.caltech.edu/CaltechTHESIS:10262010-082537998",
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    url = "https://resolver.caltech.edu/CaltechETD:etd-01132006-152609",
    id = "record",
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    url = "https://resolver.caltech.edu/CaltechTHESIS:03022011-131111881",
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