As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devices on critical paths forces designers to reduce clock speed in order to meet timing. For an important and emerging class of applications that target energy-minimal operation at the cost of delay, the impact of variation-induced defects at very low voltages mandates the sizing up of transistors and operation at higher voltages to maintain functionality.
\r\n\r\nWith post-fabrication configurability, FPGAs have the opportunity to self-measure the impact of variation, determining the speed and functionality of each individual resource. Given that information, a delay-aware router can use slow devices on non-critical paths, fast devices on critical paths, and avoid known defects. By mapping each component individually and customizing designs to a component's unique physical characteristics, we demonstrate that we can eliminate delay margins and reduce energy margins caused by variation.
\r\n\r\nTo quantify the potential benefit we might gain from component-specific mapping, we first measure the margins associated with parameter variation, and then focus primarily on the energy benefits of FPGA delay-aware routing over a wide range of predictive technologies (45 nm--12 nm) for the Toronto20 benchmark set. We show that relative to delay-oblivious routing, delay-aware routing without any significant optimizations can reduce minimum energy/operation by 1.72x at 22 nm. We demonstrate how to construct an FPGA architecture specifically tailored to further increase the minimum energy savings of component-specific mapping by using the following techniques: power gating, gate sizing, interconnect sparing, and LUT remapping. With all optimizations considered we show a minimum energy/operation savings of 2.66x at 22 nm, or 1.68--2.95x when considered across 45--12 nm. As there are many challenges to measuring resource delays and mapping per chip, we discuss methods that may make component-specific mapping more practical. We demonstrate that a simpler, defect-aware routing achieves 70% of the energy savings of delay-aware routing. Finally, we show that without variation tolerance, scaling from 16 nm to 12 nm results in a net increase in minimum energy/operation; component-specific mapping, however, can extend minimum energy/operation scaling to 12 nm and possibly beyond.
\r\n", "doi": "10.7907/358S-CW22", "publication_date": "2013", "thesis_type": "phd", "thesis_year": "2013" }, { "id": "thesis:7188", "collection": "thesis", "collection_id": "7188", "cite_using_url": "https://resolver.caltech.edu/CaltechTHESIS:08192012-145253489", "type": "thesis", "title": "GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms", "author": [ { "family_name": "DeLorimier", "given_name": "Michael John", "clpid": "DeLorimier-Michael-John" } ], "thesis_advisor": [ { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" }, { "family_name": "Desbrun", "given_name": "Mathieu", "clpid": "Desbrun-M" } ], "thesis_committee": [ { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Chandy", "given_name": "K. Mani", "clpid": "Chandy-K-M" }, { "family_name": "Meiron", "given_name": "Daniel I.", "clpid": "Meiron-D-I" }, { "family_name": "Shrobe", "given_name": "Howard", "clpid": "Shrobe-H" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "We introduce a domain-specific language, GRAph Parallel Actor Language, that enables parallel graph algorithms to be written in a natural, high-level form. GRAPAL is based on our GraphStep compute model, which enables a wide range of parallel graph algorithms that are high-level, deterministic, free from race conditions, and free from deadlock. Programs written in GRAPAL are easy for a compiler and runtime to map to efficient parallel field programmable gate array (FPGA) implementations. We show that the GRAPAL compiler can verify that the structure of operations conforms to the GraphStep model. We allocate many small processing elements in each FPGA that take advantage of the high on-chip memory bandwidth (5x the sequential processor) and process one graph edge per clock cycle per processing element. We show how to automatically choose parameters for the logic architecture so the high-level GRAPAL programming model is independent of the target FPGA architecture. We compare our GRAPAL applications mapped to a platform with four 65 nm Virtex-5 SX95T FPGAs to sequential programs run on a single 65 nm Xeon 5160. Our implementation achieves a total mean speedup of 8x with a maximum speedup of 28x. The speedup per chip is 2x with a maximum of 7x. The ratio of energy used by our GRAPAL implementation over the sequential implementation has a mean of 1/10 with a minimum of 1/80.", "doi": "10.7907/M3TW-7Y53", "publication_date": "2013", "thesis_type": "phd", "thesis_year": "2013" }, { "id": "thesis:6159", "collection": "thesis", "collection_id": "6159", "cite_using_url": "https://resolver.caltech.edu/CaltechTHESIS:10262010-082537998", "primary_object_url": { "basename": "submit_oct26.pdf", "content": "final", "filesize": 4906533, "license": "other", "mime_type": "application/pdf", "url": "/6159/1/submit_oct26.pdf", "version": "v5.0.0" }, "type": "thesis", "title": "SPICE\u00b2: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator\r ", "author": [ { "family_name": "Kapre", "given_name": "Nachiket Ganesh", "orcid": "0000-0002-2187-0406", "clpid": "Kapre-Nachiket-Ganesh" } ], "thesis_advisor": [ { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" } ], "thesis_committee": [ { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Meiron", "given_name": "Daniel I.", "clpid": "Meiron-D-I" }, { "family_name": "Bruck", "given_name": "Jehoshua", "clpid": "Bruck-J" }, { "family_name": "Trimberger", "given_name": "Steven", "clpid": "Trimberger-S" }, { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "Spatial processing of sparse, irregular floating-point computation using a single FPGA enables up to an order of magnitude speedup (mean 2.8X speedup) over a conventional microprocessor for the SPICE circuit simulator. We deliver this speedup using a hybrid parallel architecture that spatially implements the heterogeneous forms of parallelism available in SPICE. We decompose SPICE into its three constituent phases: Model-Evaluation, Sparse Matrix-Solve, and Iteration Control and parallelize each phase independently. We exploit data-parallel device evaluations in the Model-Evaluation phase, sparse dataflow parallelism in the Sparse Matrix-Solve phase and compose the complete design in streaming fashion. We name our parallel architecture SPICE\u00b2: Spatial Processors Interconnected for Concurrent Execution for accelerating the SPICE circuit simulator. We program the parallel architecture with a high-level, domain-specific framework that identifies, exposes and exploits parallelism available in the SPICE circuit simulator. This design is optimized with an auto-tuner that can scale the design to use larger FPGA capacities without expert intervention and can even target other parallel architectures with the assistance of automated code-generation. This FPGA architecture is able to outperform conventional processors due to a combination of factors including high utilization of statically-scheduled resources, low-overhead dataflow scheduling of fine-grained tasks, and overlapped processing of the control algorithms.
\r\n\r\nWe demonstrate that we can independently accelerate Model-Evaluation by a mean factor of 6.5X(1.4--23X) across a range of non-linear device models and Matrix-Solve by 2.4X(0.6--13X) across various benchmark matrices while delivering a mean combined speedup of 2.8X(0.2--11X) for the two together when comparing a Xilinx Virtex-6 LX760 (40nm) with an Intel Core i7 965 (45nm). With our high-level framework, we can also accelerate Single-Precision Model-Evaluation on NVIDIA GPUs, ATI GPUs, IBM Cell, and Sun Niagara 2 architectures.
\r\n\r\nWe expect approaches based on exploiting spatial parallelism to become important as frequency scaling slows down and modern processing architectures turn to parallelism (\\eg multi-core, GPUs) due to constraints of power consumption. This thesis shows how to express, exploit and optimize spatial parallelism for an important class of problems that are challenging to parallelize.
\r\n", "doi": "10.7907/QVZR-VB52", "publication_date": "2011", "thesis_type": "phd", "thesis_year": "2011" }, { "id": "thesis:5690", "collection": "thesis", "collection_id": "5690", "cite_using_url": "https://resolver.caltech.edu/CaltechTHESIS:04052010-152122284", "type": "thesis", "title": "Algorithms and Techniques for Conquering Extreme Physical Variation in Bottom-Up Nanoscale Systems", "author": [ { "family_name": "Gojman", "given_name": "Benjamin", "clpid": "Gojman-Benjamin" } ], "thesis_advisor": [ { "family_name": "Desbrun", "given_name": "Mathieu", "clpid": "Desbrun-M" }, { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" } ], "thesis_committee": [ { "family_name": "None", "given_name": "None" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "Nanowire building blocks provide a promising path to small feature size and thus the ability to more densely pack logic. However, the small feature size and novel, bottom-up manufacturing process will exhibit extreme variation and produce many devices that operate outside acceptable operating ranges. One-mapping-fits-all, prefabrication assignment of logical functions to physical transistors that exhibit high threshold variation will not work\u2014combining the wide range of physical variation in transistor threshold voltage with the wide range of fanouts in the design produces an unworkably large composite range of possible delays. Nonetheless, by carefully matching the fanout of each net to the physical threshold voltages of devices after fabrication, it is possible to reduce the net range of path delays sufficiently to achieve high system yield. Characterization of the complete threshold voltage distribution present in the system can be measured at a rate of 108 resources per second by augmenting the system with voltage comparison mechanisms. By adding a modest amount of extra resources, we achieve 100% yield for systems built out of devices with 38% variation, the ITRS prediction for threshold variation in 5 nm transistors. Moreover, for these systems, we maintain delay, energy and area close to the variation-free nominal case. What\u2019s more, there is only a 10% overhead when the measurement precision is limited to ten discrete threshold voltage values.\r\n", "doi": "10.7907/BBC7-XK34", "publication_date": "2010", "thesis_type": "masters", "thesis_year": "2010" }, { "id": "thesis:320", "collection": "thesis", "collection_id": "320", "cite_using_url": "https://resolver.caltech.edu/CaltechETD:etd-01242008-012650", "primary_object_url": { "basename": "Helia_Naeimi_PhD_Thesis.pdf", "content": "final", "filesize": 1357385, "license": "other", "mime_type": "application/pdf", "url": "/320/1/Helia_Naeimi_PhD_Thesis.pdf", "version": "v2.0.0" }, "type": "thesis", "title": "Reliable Integration of Terascale Systems with Nanoscale Devices", "author": [ { "family_name": "Naeimi", "given_name": "Helia", "clpid": "Naeimi-Helia" } ], "thesis_advisor": [ { "family_name": "DeHon", "given_name": "Andre", "orcid": "0000-0001-9177-7699", "clpid": "DeHon-A" } ], "thesis_committee": [ { "family_name": "DeHon", "given_name": "Andre", "orcid": "0000-0001-9177-7699", "clpid": "DeHon-A" }, { "family_name": "Martin", "given_name": "Alain J.", "clpid": "Martin-A-J" }, { "family_name": "Heath", "given_name": "James R.", "orcid": "0000-0001-5356-4385", "clpid": "Heath-J-R" }, { "family_name": "Ho", "given_name": "Tracey C.", "clpid": "Ho-Tracey" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "Nanotechnology design has attracted considerable attention in recent years and seems to be the technology for the future generation of the electronic devices, either as scaled and more restricted conventional lithographic technology, or as emerging sublithographic technologies, such as nanowires, carbon nanotubes, NDR (Negative Differential Resistance) devices, or other nanotechnology devices. Each of these technologies provides one or more design benefits including feature-size scaling, high on\u2013off ratios, and faster devices. However, all of these techniques share their most challenging design issue: reliability. Providing reliability is becoming constantly more challenging due to increases in both the device failure rate and system complexity. This work develops techniques that make achieving reliability in such systems feasible with practical area overhead and considerable improvement in area overhead and system reliability compared to related techniques.
\r\n\r\nConventional reliability techniques focus on low defect and fault rates, i.e., single event upset (SEU). These techniques cannot simply be scaled to larger systems with more unreliable devices. If these techniques are directly applied to the high defect and fault rate of the nanotechnology regime, they suffer impractically high overhead, or they may not achieve the desired reliability. Our approach in this thesis exploits the following design patterns to achieve a considerable area reduction compared to related works and achieve high reliability:
\r\n(1) Fine-grained reliability: In this technique, the system is partitioned into fine\u2013grained blocks, and the reliability is provided for each block. This technique is used to contain the area overhead and bound the impact on the throughput.
\r\n(2) Using alternative resources: This technique improves the design quality by sparing other resources when system is tight on one resource. In our work we replace some of the spacial redundancies with temporal redundancy to limit the area overhead. We further improve the system throughput to limit the throughput cost as well.
\r\n(3) Defect pattern matching: With this techniques, the defective resources are located and the design is reconfigured considering the defect pattern of the chip. Then the design configuration is mapped to the chip. This technique isolates the defective resources and make use of most of defect free resources.
\r\n(4) Global reliability: This technique is used to unify the reliability techniques used in different parts of the system. When using one unified technique to protect the system, the area overhead provided to protect one resource can be reused to protect other resources as well.
In the present work, we report considerable improvement in the area overhead using the above techniques. We show that using Fine-Grained Reliability, Alternative Resources, and Defect Pattern Matching, high permanent defect rates (e.g., 10%) which is the result of imperfect manufacturing can be tolerated with moderate area overhead (about 30% on average for typical designs). Again Using Alternative Resources and Fine-Grained Reliability improve the area overhead of the transient fault-tolerant designs by close to an order of magnitude compared to recent reliable works. Finally we report a fully reliable memory system that employs a Global Reliability scheme to tolerate permanent defects and transient faults, both in the memory and in the supporting logic and still achieves 100 Gbit/cm2 density for fault rate of 10\u221218 errors per bit per cycle and 10% junction defect rate.
", "doi": "10.7907/P842-7B49", "publication_date": "2008", "thesis_type": "phd", "thesis_year": "2008" }, { "id": "thesis:2335", "collection": "thesis", "collection_id": "2335", "cite_using_url": "https://resolver.caltech.edu/CaltechETD:etd-05312006-164103", "primary_object_url": { "basename": "final.pdf", "content": "final", "filesize": 1407781, "license": "other", "mime_type": "application/pdf", "url": "/2335/1/final.pdf", "version": "v3.0.0" }, "type": "thesis", "title": "Time-Multiplexed FPGA Overlay Networks on Chip", "author": [ { "family_name": "Mehta", "given_name": "Nikil", "clpid": "Mehta-Nikil" } ], "thesis_advisor": [ { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" } ], "thesis_committee": [ { "family_name": "Unknown", "given_name": "Unknown" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "How do we design a communication network for processing elements (PEs) on a single chip that minimizes application communication time and area? In designing such a network it is essential to use a network communication pattern that matches application communication and area requirements. This report characterizes the design space of a particular communication pattern for networks on chip: Time-Multiplexed Interconnect. In contrast to more commonly used packet-switched networks, which route communication dynamically, time-multiplexed networks schedule all possible communication prior to runtime with an offline router. We describe how to build well engineered, highly scalable time-multiplexed FPGA networks in terms of topology selection, routing algorithm design and hardware design that operate on a Xilinx XC2V6000-4 at 166MHz. To benchmark our networks we use real, communication rich applications instead of generating synthetic traffic. We show that over all areas (10K\u201310M slices) and over all applications the best \"one topology fits all\" is Butterfly Fat Tree (BFT) with c = 1, p = 0.5, which requires, in the worst case, 6.1x as many cycles to route communication than the optimal topology. We compare time-multiplexing to packet-switching, and show that on average, over all applications for all equivalent topologies, online packet-switched communication requires 1.5x as many cycles to route as offline time-multiplexed scheduling. When applying designs to equivalent area, for areas <100K slices packet-switching typically outperforms time-multiplexing, but at >100K slices packet-switching requires up to 3.4x as many cycles to route as time-multiplexing in the worst case. Finally, for equivalent, large networks (>100 PEs) time-multiplexing outperforms packet-switching for communication loads where greater than 10% of all logical links are active. This demonstrates that well designed time-multiplexed FPGA overlay networks can deliver performance and area efficiency exceeding that of packet-switched networks.", "doi": "10.7907/WZTS-XR26", "publication_date": "2006", "thesis_type": "masters", "thesis_year": "2006" }, { "id": "thesis:2334", "collection": "thesis", "collection_id": "2334", "cite_using_url": "https://resolver.caltech.edu/CaltechETD:etd-05312006-164059", "primary_object_url": { "basename": "draft.pdf", "content": "final", "filesize": 1076324, "license": "other", "mime_type": "application/pdf", "url": "/2334/1/draft.pdf", "version": "v3.0.0" }, "type": "thesis", "title": "Packet-Switched On-Chip FPGA Overlay Networks", "author": [ { "family_name": "Kapre", "given_name": "Nachiket Ganesh", "orcid": "0000-0002-2187-0406", "clpid": "Kapre-Nachiket-Ganesh" } ], "thesis_advisor": [ { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" } ], "thesis_committee": [ { "family_name": "Unknown", "given_name": "Unknown" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "As we scale to larger chip capacities, it becomes possible to map large, concurrent applications to programmable fabrics. These applications often have irregular and dynamic communication requirements. Packet-switched networks provide efficient implementations for such applications on these fabrics. In this research, we show how to engineer high-performance packet-switched on-chip networks and provide quantitative comparisons between different kinds of these networks. We analyse different network topologies and justify selection of topologies based on experimental results. We investigate packet-switched and time-multiplexed styles of routing and provide guidance on which style is appropriate for which application.", "doi": "10.7907/8NFZ-4Y29", "publication_date": "2006", "thesis_type": "masters", "thesis_year": "2006" }, { "id": "thesis:1624", "collection": "thesis", "collection_id": "1624", "cite_using_url": "https://resolver.caltech.edu/CaltechETD:etd-05052005-164226", "primary_object_url": { "basename": "main.pdf", "content": "final", "filesize": 637817, "license": "other", "mime_type": "application/pdf", "url": "/1624/1/main.pdf", "version": "v3.0.0" }, "type": "thesis", "title": "A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design", "author": [ { "family_name": "Naeimi", "given_name": "Helia", "clpid": "Naeimi-Helia" } ], "thesis_advisor": [ { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" } ], "thesis_committee": [ { "family_name": "Unknown", "given_name": "Unknown" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "Recent developments suggest both plausible fabrication techniques and viable architectures for building sublithographic Programmable Logic Arrays using molecular-scale wires and switches. Designs at this scale will see much higher defect rates than in conventional lithography. However, these defects need not be an impediment to programmable logic design at this scale.
\r\n\r\nWe introduce a strategy for tolerating defective crosspoints in PLA architecture. We develop a linear-time, greedy algorithm for mapping PLA logic around crosspoint defects. The mapping algorithm matches the PLA logic to the defect configuration of each device.
\r\n\r\nWe note that P-term fanin must be bounded to guarantee low overhead mapping and develop analytical guidelines for bounding fanin. We further quantify analytical and empirical mapping overhead rates. Including fanin bounding, our greedy mapping algorithm maps a large set of benchmark designs with 13% average overhead for random junction defect rates as high as 20%.
", "doi": "10.7907/Z5AS-8A57", "publication_date": "2005", "thesis_type": "masters", "thesis_year": "2005" }, { "id": "thesis:1776", "collection": "thesis", "collection_id": "1776", "cite_using_url": "https://resolver.caltech.edu/CaltechETD:etd-05132005-144347", "primary_object_url": { "basename": "smvm_thesis.pdf", "content": "final", "filesize": 552592, "license": "other", "mime_type": "application/pdf", "url": "/1776/1/smvm_thesis.pdf", "version": "v3.0.0" }, "type": "thesis", "title": "Floating-Point Sparse Matrix-Vector Multiply for FPGAs", "author": [ { "family_name": "deLorimier", "given_name": "Michael John", "clpid": "deLorimier-Michael-John" } ], "thesis_advisor": [ { "family_name": "DeHon", "given_name": "Andre", "clpid": "DeHon-A" } ], "thesis_committee": [ { "family_name": "Unknown", "given_name": "Unknown" } ], "local_group": [ { "literal": "div_eng" } ], "abstract": "Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not deliver near their peak floating-point performance on efficient algorithms that use the Sparse Matrix-Vector Multiply (SMVM) kernel. In fact, microprocessors rarely achieve 33% of their peak floating-point performance when computing SMVM. We develop and analyze a scalable SMVM implementation on modern FPGAs and show that it can sustain high throughput, near peak, floating-point performance. Our implementation consists of logic design as well as scheduling and data placement techniques. For benchmark matrices from the Matrix Market Suite we project 1.5 double precision Gflops/FPGA for a single VirtexII-6000-4 and 12 double precision Gflops for 16 Virtex IIs (750 Mflops/FPGA). We also analyze the asymptotic efficiency of our architecture as parallelism scales using a constant rent-parameter matrix model. This demonstrates that our data placement techniques provide an asymptotic scaling benefit.
\r\n\r\nWhile FPGA performance is attractive, higher performance is possible if we re-balance the hardware resources in FPGAs with embedded memories. We show that sacrificing half the logic area for memory area rarely degrades performance and improves performance for large matrices, by up to 5 times. We also 0 the performance effect of adding custom floating-point using a simple area model to preserve total chip area. Sacrificing logic for memory and custom floating-point units increases single FPGA performance to 5 double precision Gflops.
", "doi": "10.7907/FCCD-FA51", "publication_date": "2005", "thesis_type": "masters", "thesis_year": "2005" } ]