<h1>DeHon, Andre</h1>
<h2>Book Chapter from <a href="https://data.caltech.edu">CaltechTHESIS advisor</a></h2>
<ul>
<li>Mehta, Nikil (2013) <a href="https://resolver.caltech.edu/CaltechTHESIS:10072012-230900231">An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping</a>; <a href="https://doi.org/10.7907/358S-CW22">10.7907/358S-CW22</a></li>
<li>DeLorimier, Michael John (2013) <a href="https://resolver.caltech.edu/CaltechTHESIS:08192012-145253489">GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms</a>; <a href="https://doi.org/10.7907/M3TW-7Y53">10.7907/M3TW-7Y53</a></li>
<li>Kapre, Nachiket Ganesh (2011) <a href="https://resolver.caltech.edu/CaltechTHESIS:10262010-082537998">SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator
</a>; <a href="https://doi.org/10.7907/QVZR-VB52">10.7907/QVZR-VB52</a></li>
<li>Gojman, Benjamin (2010) <a href="https://resolver.caltech.edu/CaltechTHESIS:04052010-152122284">Algorithms and Techniques for Conquering Extreme Physical Variation in Bottom-Up Nanoscale Systems</a>; <a href="https://doi.org/10.7907/BBC7-XK34">10.7907/BBC7-XK34</a></li>
<li>Naeimi, Helia (2008) <a href="https://resolver.caltech.edu/CaltechETD:etd-01242008-012650">Reliable Integration of Terascale Systems with Nanoscale Devices</a>; <a href="https://doi.org/10.7907/P842-7B49">10.7907/P842-7B49</a></li>
<li>Mehta, Nikil (2006) <a href="https://resolver.caltech.edu/CaltechETD:etd-05312006-164103">Time-Multiplexed FPGA Overlay Networks on Chip</a>; <a href="https://doi.org/10.7907/WZTS-XR26">10.7907/WZTS-XR26</a></li>
<li>Kapre, Nachiket Ganesh (2006) <a href="https://resolver.caltech.edu/CaltechETD:etd-05312006-164059">Packet-Switched On-Chip FPGA Overlay Networks</a>; <a href="https://doi.org/10.7907/8NFZ-4Y29">10.7907/8NFZ-4Y29</a></li>
<li>Naeimi, Helia (2005) <a href="https://resolver.caltech.edu/CaltechETD:etd-05052005-164226">A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design</a>; <a href="https://doi.org/10.7907/Z5AS-8A57">10.7907/Z5AS-8A57</a></li>
<li>deLorimier, Michael John (2005) <a href="https://resolver.caltech.edu/CaltechETD:etd-05132005-144347">Floating-Point Sparse Matrix-Vector Multiply for FPGAs</a>; <a href="https://doi.org/10.7907/FCCD-FA51">10.7907/FCCD-FA51</a></li>
</ul>