<h1>DeHon, Andre</h1>
<h2>Combined from <a href="https://authors.library.caltech.edu">CaltechAUTHORS</a></h2>
<ul>
<li>Gojman, Benjamin and Nalmela, Sirisha, el al. (2014) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20150121-071331821">GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction</a>; ACM Transactions on Reconfigurable Technology Systems; Vol. 7; No. 4; Art. No. 32; <a href="https://doi.org/10.1145/2597889">10.1145/2597889</a></li>
<li>Gojman, Benjamin and Nalmela, Sirisha, el al. (2013) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20130328-131459182">GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction</a>; ISBN 978-1-4503-1887-7; Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays; 81-90; <a href="https://doi.org/10.1145/2435264.2435281">10.1145/2435264.2435281</a></li>
<li>Mehta, Nikil and Rubin, Raphael, el al. (2012) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20120521-105703473">Limit study of energy &amp; delay benefits of component-specific routing</a>; ISBN 978-1-4503-1155-7; Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays; 97-106; <a href="https://doi.org/10.1145/2145694.2145710">10.1145/2145694.2145710</a></li>
<li>Kapre, Nachiket and DeHon, André (2009) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20100707-100125364">Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors</a>; ISBN 978-1-4244-3891-4; FPL:  2009 International Conference on Field Programmable Logic and Applications; 65-72; <a href="https://doi.org/10.1109/FPL.2009.5272548">10.1109/FPL.2009.5272548</a></li>
<li>Naeimi, Helia and DeHon, André (2009) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20090831-143856470">Fault Secure Encoder and Decoder for NanoMemory Applications</a>; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 17; No. 4; 473-486; <a href="https://doi.org/10.1109/TVLSI.2008.2009217">10.1109/TVLSI.2008.2009217</a></li>
<li>Papadantonakis, Karl and Kapre, Nachiket, el al. (2009) <a href="https://resolver.caltech.edu/CaltechAUTHORS:PAPieeetc09">Pipelining Saturated Accumulation</a>; IEEE Transactions on Computers; Vol. 58; No. 2; 208-219; <a href="https://doi.org/10.1109/TC.2008.110">10.1109/TC.2008.110</a></li>
<li>Kapre, Nachiket and DeHon, André (2009) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20100507-150521265">Accelerating SPICE Model-Evaluation using FPGAs</a>; ISBN 978-0-7695-3716-0; Field Programmable Custom Computing Machines, 2009; 37-44; <a href="https://doi.org/10.1109/FCCM.2009.14">10.1109/FCCM.2009.14</a></li>
<li>Naeimi, Helia and DeHon, André (2008) <a href="https://resolver.caltech.edu/CaltechAUTHORS:NAEnanot08">Fault-tolerant sub-lithographic design with rollback recovery</a>; Nanotechnology; Vol. 19; No. 11; 115708; <a href="https://doi.org/10.1088/0957-4484/19/11/115708">10.1088/0957-4484/19/11/115708</a></li>
<li>Naeimi, Helia and DeHon, André (2007) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110817-152509198">Fault Secure Encoder and Decoder for Memory Applications</a>; ISBN 978-0-7695-2885-4; 2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems; 409-417; <a href="https://doi.org/10.1109/DFT.2007.54">10.1109/DFT.2007.54</a></li>
<li>Kapre, Nachiket and DeHon, André (2007) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20100923-111814269">Optimistic Parallelization of Floating-Point Accumulation</a>; ISBN 978-0-7695-2854-0; 18th IEEE Symposium on Computer Arithmetic; 205-216; <a href="https://doi.org/10.1109/ARITH.2007.25">10.1109/ARITH.2007.25</a></li>
<li>Nomura, Kumiko and DeHon, André, el al. (2006) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110720-093755059">Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices</a>; ISBN 978-1-4244-0390-5; 2006 1st International Conference on Nano-Networks and Workshops; 72-76; <a href="https://doi.org/10.1109/NANONET.2006.346226">10.1109/NANONET.2006.346226</a></li>
<li>Savage, John E. and Rachlin, Eric, el al. (2006) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161213-174431809">Radial addressing of nanowires</a>; ACM Journal on Emerging Technologies in Computing Systems (JETC); Vol. 2; No. 2; 129-154; <a href="https://doi.org/10.1145/1148015.1148018">10.1145/1148015.1148018</a></li>
<li>Wrighton, Michael G. and DeHon, André M. (2006) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20170109-150041807">SAT-based optimal hypergraph partitioning with replication</a>; ISBN 0-7803-9451-8; Asia and South Pacific Conference on Design Automation, 2006; 789-795; <a href="https://doi.org/10.1109/ASPDAC.2006.1594782">10.1109/ASPDAC.2006.1594782</a></li>
<li>deLorimier, Michael and Kapre, Nachiket, el al. (2006) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110223-132654232">GraphStep: A System Architecture for Sparse-Graph Algorithms</a>; ISBN 0-7695-2661-6; FCCM 2006: 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 143-151; <a href="https://doi.org/10.1109/FCCM.2006.45">10.1109/FCCM.2006.45</a></li>
<li>Gojman, Benjamin and Rubin, Raphael, el al. (2006) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110630-080922757">3D Nanowire-Based Programmable Logic</a>; ISBN 978-1-4244-0390-5; 2006 1st International Conference on Nano-Networks and Workshops; 54-58; <a href="https://doi.org/10.1109/NANONET.2006.346223">10.1109/NANONET.2006.346223</a></li>
<li>Kapre, Nachiket and Mehta, Nikil, el al. (2006) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110225-090013910">Packet Switched vs. Time Multiplexed FPGA
Overlay Networks</a>; ISBN 0-7695-2661-6; FCCM 2006: 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 205-216; <a href="https://doi.org/10.1109/FCCM.2006.55">10.1109/FCCM.2006.55</a></li>
<li>Papadantonakis, Karl and Kapre, Nachiket, el al. (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110816-113648980">Pipelining saturated accumulation</a>; ISBN 0-7803-9407-0; 2005 IEEE International Conference on Field-Programmable Technology; 19-26; <a href="https://doi.org/10.1109/FPT.2005.1568519">10.1109/FPT.2005.1568519</a></li>
<li>DeHon, André (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05b">Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches</a>; IEEE Transactions on Nanotechnology; Vol. 4; No. 6; 681-687; <a href="https://doi.org/10.1109/TNANO.2005.858587">10.1109/TNANO.2005.858587</a></li>
<li>DeHon, André and Likharev, Konstantin K. (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110815-092459485">Hybrid CMOS/Nanoelectronic Digital Circuits:
Devices, Architectures, and Design Automation</a>; ISBN 0-7803-9254-X; ICCAD-2005 : International Conference on Computer Aided Design; 375-382; <a href="https://doi.org/10.1109/ICCAD.2005.1560097">10.1109/ICCAD.2005.1560097</a></li>
<li>DeHon, André and Naeimi, Helia (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeedtc05">Seven strategies for tolerating highly defective fabrication</a>; IEEE Design and Test of Computers; Vol. 22; No. 4; 306-315; <a href="https://doi.org/10.1109/MDT.2005.94">10.1109/MDT.2005.94</a></li>
<li>Dehon, André (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20160420-100045980">Nanowire-Based Programmable Architectures</a>; ACM Journal on Emerging Technologies in Computing Systems (JETC); Vol. 1; No. 2; 109-162; <a href="https://doi.org/10.1145/1084748.1084750">10.1145/1084748.1084750</a></li>
<li>DeHon, André and Goldstein, Seth Copen, el al. (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05a">Nonphotolithographic nanoscale memory density prospects</a>; IEEE Transactions on Nanotechnology; Vol. 4; No. 2; 215-228; <a href="https://doi.org/10.1109/TNANO.2004.837849">10.1109/TNANO.2004.837849</a></li>
<li>deLorimier, Michael and DeHon, André (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161006-130031306">Floating-Point Sparse Matrix-Vector Multiply for FPGAs</a>; ISBN 1-59593-029-9; FPGA '05 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays; 75-85; <a href="https://doi.org/10.1145/1046192.1046203">10.1145/1046192.1046203</a></li>
<li>DeHon, André (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20160419-162745354">Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays</a>; ISBN 1-59593-029-9; Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05); 127-137; <a href="https://doi.org/10.1145/1046192.1046210">10.1145/1046192.1046210</a></li>
<li>Naeimi, Helia and DeHon, André (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110822-103525220">A greedy algorithm for tolerating defective crosspoints in nanoPLA design</a>; ISBN 0-7803-8651-5; 2004 IEEE International Conference on Field-Programmable Technology; 49-56; <a href="https://doi.org/10.1109/FPT.2004.1393250">10.1109/FPT.2004.1393250</a></li>
<li>DeHon, André and Rubin, Raphael (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04a">Design of FPGA interconnect for multilevel metallization</a>; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 12; No. 10; 1038-1050; <a href="https://doi.org/10.1109/TVLSI.2004.827562">10.1109/TVLSI.2004.827562</a></li>
<li>DeHon, André (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04b">Unifying mesh- and tree-based programmable interconnect</a>; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 12; No. 10; 1051-1065; <a href="https://doi.org/10.1109/TVLSI.2004.834237">10.1109/TVLSI.2004.834237</a></li>
<li>DeHon, André and Adams, Joshua, el al. (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20110817-151253900">Design patterns for reconfigurable computing</a>; ISBN 0-7695-2230-0; 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 13-23; <a href="https://doi.org/10.1109/FCCM.2004.29">10.1109/FCCM.2004.29</a></li>
<li>DeHon, André and Wilson, Michael J. (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161006-125146350">Nanowire-Based Sublithographic Programmable Logic Arrays</a>; ISBN 1-58113-829-6; FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays; 123-132; <a href="https://doi.org/10.1145/968280.968299">10.1145/968280.968299</a></li>
<li>DeHon, André and Hutchings, Brad, el al. (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161005-174825781">What is the Right Model for Programming and Using Modern FPGAs?</a>; ISBN 1-58113-829-6; FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays; 119; <a href="https://doi.org/10.1145/968280.968281">10.1145/968280.968281</a></li>
<li>Kapre, Nachiket and Walther, Dirk B., el al. (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20130816-103300863">Saliency on a chip: a digital approach with an FPGA</a>; The Neuromorphic Engineer; Vol. 1; No. 2; 9-11</li>
<li>DeHon, André and Lincoln, Patrick, el al. (2003) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03b">Stochastic assembly of sublithographic nanoscale interfaces</a>; IEEE Transactions on Nanotechnology; Vol. 2; No. 3; 165-174; <a href="https://doi.org/10.1109/TNANO.2003.816658">10.1109/TNANO.2003.816658</a></li>
<li>DeHon, André (2003) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03a">Array-based architecture for FET-based, nanoscale electronics</a>; IEEE Transactions on Nanotechnology; Vol. 2; No. 1; 23-32; <a href="https://doi.org/10.1109/TNANO.2003.808508">10.1109/TNANO.2003.808508</a></li>
<li>Rubin, Raphael and DeHon, André (2003) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161213-164304748">Design of FPGA interconnect for multilevel metalization</a>; ISBN 1-58113-651-X; FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; 154-163; <a href="https://doi.org/10.1145/611817.611841">10.1145/611817.611841</a></li>
<li>Wrighton, Michael G. and DeHon, André M. (2003) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20170109-150810119">Hardware-assisted simulated annealing with application for fast FPGA placement</a>; ISBN 1-58113-651-X; FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; 33-42; <a href="https://doi.org/10.1145/611817.611824">10.1145/611817.611824</a></li>
<li>Huang, Randy and Wawrzynek, John, el al. (2003) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161107-154348196">Stochastic, spatial routing for hypergraphs, trees, and meshes</a>; ISBN 1-58113-651-X; FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; 78-87; <a href="https://doi.org/10.1145/611817.611830">10.1145/611817.611830</a></li>
<li>Butts, Michael and DeHon, André, el al. (2002) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20160812-112140221">Molecular electronics: devices, systems and tools for gigagate, gigabit chips</a>; ISBN 0-7803-7607-2; IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002; 443-440; <a href="https://doi.org/10.1109/ICCAD.2002.1167569">10.1109/ICCAD.2002.1167569</a></li>
<li>DeHon, André (2002) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20200127-123636117">Very Large Scale Spatial Computing</a>; ISBN 978-3-540-44311-7; Unconventional Models of Computation; 27-37; <a href="https://doi.org/10.1007/3-540-45833-6_3">10.1007/3-540-45833-6_3</a></li>
<li>Markovskiy, Yury and Caspi, Eylon, el al. (2002) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161129-173323435">Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine</a>; ISBN 1-58113-452-5; FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays; 196-205; <a href="https://doi.org/10.1145/503048.503077">10.1145/503048.503077</a></li>
<li>DeHon, André (2000) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHcomputer00">The density advantage of configurable computing</a>; Computer; Vol. 33; No. 4; 41-49; <a href="https://doi.org/10.1109/2.839320">10.1109/2.839320</a></li>
<li>Mangione-Smith, William H. and Hutchings, Brad, el al. (1997) <a href="https://resolver.caltech.edu/CaltechAUTHORS:MANcompute97">Seeking solutions in configurable computing</a>; Computer; Vol. 30; No. 12; 38-43; <a href="https://doi.org/10.1109/2.642810">10.1109/2.642810</a></li>
</ul>