@article{https://resolver.caltech.edu/CaltechAUTHORS:20150121-071331821, title = "GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction", journal = "ACM Transactions on Reconfigurable Technology Systems", year = "2014", url = "https://resolver.caltech.edu/CaltechAUTHORS:20150121-071331821", id = "record", issn = "1936-7406", doi = "10.1145/2597889", volume = "7" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20130328-131459182, title = "Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays", chapter = "GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction", year = "2013", url = "https://resolver.caltech.edu/CaltechAUTHORS:20130328-131459182", id = "record", isbn = "978-1-4503-1887-7", doi = "10.1145/2435264.2435281" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20120521-105703473, title = "Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays", chapter = "Limit study of energy \& delay benefits of component-specific routing", year = "2012", url = "https://resolver.caltech.edu/CaltechAUTHORS:20120521-105703473", id = "record", isbn = "978-1-4503-1155-7", doi = "10.1145/2145694.2145710" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20100707-100125364, title = "FPL: 2009 International Conference on Field Programmable Logic and Applications", chapter = "Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors", year = "2009", url = "https://resolver.caltech.edu/CaltechAUTHORS:20100707-100125364", id = "record", isbn = "978-1-4244-3891-4", doi = "10.1109/FPL.2009.5272548" } @article{https://resolver.caltech.edu/CaltechAUTHORS:20090831-143856470, title = "Fault Secure Encoder and Decoder for NanoMemory Applications", journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", year = "2009", url = "https://resolver.caltech.edu/CaltechAUTHORS:20090831-143856470", id = "record", issn = "1063-8210", doi = "10.1109/TVLSI.2008.2009217", volume = "17" } @article{https://resolver.caltech.edu/CaltechAUTHORS:PAPieeetc09, title = "Pipelining Saturated Accumulation", journal = "IEEE Transactions on Computers", year = "2009", url = "https://resolver.caltech.edu/CaltechAUTHORS:PAPieeetc09", id = "record", issn = "0018-9340", doi = "10.1109/TC.2008.110", volume = "58" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20100507-150521265, title = "Field Programmable Custom Computing Machines, 2009", chapter = "Accelerating SPICE Model-Evaluation using FPGAs", year = "2009", url = "https://resolver.caltech.edu/CaltechAUTHORS:20100507-150521265", id = "record", isbn = "978-0-7695-3716-0", doi = "10.1109/FCCM.2009.14" } @article{https://resolver.caltech.edu/CaltechAUTHORS:NAEnanot08, title = "Fault-tolerant sub-lithographic design with rollback recovery", journal = "Nanotechnology", year = "2008", url = "https://resolver.caltech.edu/CaltechAUTHORS:NAEnanot08", id = "record", issn = "0957-4484", doi = "10.1088/0957-4484/19/11/115708", volume = "19" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110817-152509198, title = "2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems", chapter = "Fault Secure Encoder and Decoder for Memory Applications", year = "2007", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110817-152509198", id = "record", isbn = "978-0-7695-2885-4", doi = "10.1109/DFT.2007.54" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20100923-111814269, title = "18th IEEE Symposium on Computer Arithmetic", chapter = "Optimistic Parallelization of Floating-Point Accumulation", year = "2007", url = "https://resolver.caltech.edu/CaltechAUTHORS:20100923-111814269", id = "record", isbn = "978-0-7695-2854-0", doi = "10.1109/ARITH.2007.25" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110720-093755059, title = "2006 1st International Conference on Nano-Networks and Workshops", chapter = "Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices", year = "2006", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110720-093755059", id = "record", isbn = "978-1-4244-0390-5", doi = "10.1109/NANONET.2006.346226" } @article{https://resolver.caltech.edu/CaltechAUTHORS:20161213-174431809, title = "Radial addressing of nanowires", journal = "ACM Journal on Emerging Technologies in Computing Systems (JETC)", year = "2006", url = "https://resolver.caltech.edu/CaltechAUTHORS:20161213-174431809", id = "record", issn = "1550-4832", doi = "10.1145/1148015.1148018", volume = "2" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20170109-150041807, title = "Asia and South Pacific Conference on Design Automation, 2006", chapter = "SAT-based optimal hypergraph partitioning with replication", year = "2006", url = "https://resolver.caltech.edu/CaltechAUTHORS:20170109-150041807", id = "record", isbn = "0-7803-9451-8", doi = "10.1109/ASPDAC.2006.1594782" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110225-090013910, title = "FCCM 2006: 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines", chapter = "Packet Switched vs. Time Multiplexed FPGA Overlay Networks", year = "2006", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110225-090013910", id = "record", isbn = "0-7695-2661-6", doi = "10.1109/FCCM.2006.55" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110630-080922757, title = "2006 1st International Conference on Nano-Networks and Workshops", chapter = "3D Nanowire-Based Programmable Logic", year = "2006", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110630-080922757", id = "record", isbn = "978-1-4244-0390-5", doi = "10.1109/NANONET.2006.346223" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110223-132654232, title = "FCCM 2006: 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines", chapter = "GraphStep: A System Architecture for Sparse-Graph Algorithms", year = "2006", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110223-132654232", id = "record", isbn = "0-7695-2661-6", doi = "10.1109/FCCM.2006.45" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110816-113648980, title = "2005 IEEE International Conference on Field-Programmable Technology", chapter = "Pipelining saturated accumulation", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110816-113648980", id = "record", isbn = "0-7803-9407-0", doi = "10.1109/FPT.2005.1568519" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05b, title = "Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches", journal = "IEEE Transactions on Nanotechnology", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05b", id = "record", issn = "1536-125X", doi = "10.1109/TNANO.2005.858587", volume = "4" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110815-092459485, title = "ICCAD-2005 : International Conference on Computer Aided Design", chapter = "Hybrid CMOS/Nanoelectronic Digital Circuits: Devices, Architectures, and Design Automation", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110815-092459485", id = "record", isbn = "0-7803-9254-X", doi = "10.1109/ICCAD.2005.1560097" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHieeedtc05, title = "Seven strategies for tolerating highly defective fabrication", journal = "IEEE Design and Test of Computers", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHieeedtc05", id = "record", issn = "0740-3224", doi = "10.1109/MDT.2005.94", volume = "22" } @article{https://resolver.caltech.edu/CaltechAUTHORS:20160420-100045980, title = "Nanowire-Based Programmable Architectures", journal = "ACM Journal on Emerging Technologies in Computing Systems (JETC)", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:20160420-100045980", id = "record", issn = "1550-4832", doi = "10.1145/1084748.1084750", volume = "1" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05a, title = "Nonphotolithographic nanoscale memory density prospects", journal = "IEEE Transactions on Nanotechnology", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05a", id = "record", issn = "1536-125X", doi = "10.1109/TNANO.2004.837849", volume = "4" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20160419-162745354, title = "Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05)", chapter = "Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:20160419-162745354", id = "record", isbn = "1-59593-029-9", doi = "10.1145/1046192.1046210" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20161006-130031306, title = "FPGA '05 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays", chapter = "Floating-Point Sparse Matrix-Vector Multiply for FPGAs", year = "2005", url = "https://resolver.caltech.edu/CaltechAUTHORS:20161006-130031306", id = "record", isbn = "1-59593-029-9", doi = "10.1145/1046192.1046203" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110822-103525220, title = "2004 IEEE International Conference on Field-Programmable Technology", chapter = "A greedy algorithm for tolerating defective crosspoints in nanoPLA design", year = "2004", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110822-103525220", id = "record", isbn = "0-7803-8651-5", doi = "10.1109/FPT.2004.1393250" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04b, title = "Unifying mesh- and tree-based programmable interconnect", journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", year = "2004", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04b", id = "record", issn = "1063-8210", doi = "10.1109/TVLSI.2004.834237", volume = "12" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04a, title = "Design of FPGA interconnect for multilevel metallization", journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", year = "2004", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04a", id = "record", issn = "1063-8210", doi = "10.1109/TVLSI.2004.827562", volume = "12" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20110817-151253900, title = "12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines", chapter = "Design patterns for reconfigurable computing", year = "2004", url = "https://resolver.caltech.edu/CaltechAUTHORS:20110817-151253900", id = "record", isbn = "0-7695-2230-0", doi = "10.1109/FCCM.2004.29" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20161006-125146350, title = "FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays", chapter = "Nanowire-Based Sublithographic Programmable Logic Arrays", year = "2004", url = "https://resolver.caltech.edu/CaltechAUTHORS:20161006-125146350", id = "record", isbn = "1-58113-829-6", doi = "10.1145/968280.968299" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20161005-174825781, title = "FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays", chapter = "What is the Right Model for Programming and Using Modern FPGAs?", year = "2004", url = "https://resolver.caltech.edu/CaltechAUTHORS:20161005-174825781", id = "record", isbn = "1-58113-829-6", doi = "10.1145/968280.968281" } @article{https://resolver.caltech.edu/CaltechAUTHORS:20130816-103300863, title = "Saliency on a chip: a digital approach with an FPGA", journal = "The Neuromorphic Engineer", year = "2004", url = "https://resolver.caltech.edu/CaltechAUTHORS:20130816-103300863", id = "record", issn = "1548-5625", volume = "1" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03b, title = "Stochastic assembly of sublithographic nanoscale interfaces", journal = "IEEE Transactions on Nanotechnology", year = "2003", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03b", id = "record", issn = "1536-125X", doi = "10.1109/TNANO.2003.816658", volume = "2" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03a, title = "Array-based architecture for FET-based, nanoscale electronics", journal = "IEEE Transactions on Nanotechnology", year = "2003", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03a", id = "record", issn = "1536-125X", doi = "10.1109/TNANO.2003.808508", volume = "2" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20170109-150810119, title = "FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays", chapter = "Hardware-assisted simulated annealing with application for fast FPGA placement", year = "2003", url = "https://resolver.caltech.edu/CaltechAUTHORS:20170109-150810119", id = "record", isbn = "1-58113-651-X", doi = "10.1145/611817.611824" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20161107-154348196, title = "FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays", chapter = "Stochastic, spatial routing for hypergraphs, trees, and meshes", year = "2003", url = "https://resolver.caltech.edu/CaltechAUTHORS:20161107-154348196", id = "record", isbn = "1-58113-651-X", doi = "10.1145/611817.611830" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20161213-164304748, title = "FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays", chapter = "Design of FPGA interconnect for multilevel metalization", year = "2003", url = "https://resolver.caltech.edu/CaltechAUTHORS:20161213-164304748", id = "record", isbn = "1-58113-651-X", doi = "10.1145/611817.611841" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20160812-112140221, title = "IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002", chapter = "Molecular electronics: devices, systems and tools for gigagate, gigabit chips", year = "2002", url = "https://resolver.caltech.edu/CaltechAUTHORS:20160812-112140221", id = "record", isbn = "0-7803-7607-2", doi = "10.1109/ICCAD.2002.1167569" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20200127-123636117, title = "Unconventional Models of Computation", chapter = "Very Large Scale Spatial Computing", year = "2002", url = "https://resolver.caltech.edu/CaltechAUTHORS:20200127-123636117", id = "record", isbn = "978-3-540-44311-7", doi = "10.1007/3-540-45833-6\_3" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20161129-173323435, title = "FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays", chapter = "Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine", year = "2002", url = "https://resolver.caltech.edu/CaltechAUTHORS:20161129-173323435", id = "record", isbn = "1-58113-452-5", doi = "10.1145/503048.503077" } @article{https://resolver.caltech.edu/CaltechAUTHORS:DEHcomputer00, title = "The density advantage of configurable computing", journal = "Computer", year = "2000", url = "https://resolver.caltech.edu/CaltechAUTHORS:DEHcomputer00", id = "record", issn = "0018-9162", doi = "10.1109/2.839320", volume = "33" } @article{https://resolver.caltech.edu/CaltechAUTHORS:MANcompute97, title = "Seeking solutions in configurable computing", journal = "Computer", year = "1997", url = "https://resolver.caltech.edu/CaltechAUTHORS:MANcompute97", id = "record", issn = "0018-9162", doi = "10.1109/2.642810", volume = "30" }