DeHon, Andre

Article from CaltechAUTHORS

• Gojman, Benjamin and Nalmela, Sirisha, el al. (2014) GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction; ACM Transactions on Reconfigurable Technology Systems; Vol. 7; No. 4; Art. No. 32; 10.1145/2597889
• Naeimi, Helia and DeHon, André (2009) Fault Secure Encoder and Decoder for NanoMemory Applications; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 17; No. 4; 473-486; 10.1109/TVLSI.2008.2009217
• Papadantonakis, Karl and Kapre, Nachiket, el al. (2009) Pipelining Saturated Accumulation; IEEE Transactions on Computers; Vol. 58; No. 2; 208-219; 10.1109/TC.2008.110
• Naeimi, Helia and DeHon, André (2008) Fault-tolerant sub-lithographic design with rollback recovery; Nanotechnology; Vol. 19; No. 11; 115708; 10.1088/0957-4484/19/11/115708
• Savage, John E. and Rachlin, Eric, el al. (2006) Radial addressing of nanowires; ACM Journal on Emerging Technologies in Computing Systems (JETC); Vol. 2; No. 2; 129-154; 10.1145/1148015.1148018
• DeHon, André (2005) Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches; IEEE Transactions on Nanotechnology; Vol. 4; No. 6; 681-687; 10.1109/TNANO.2005.858587
• Dehon, André (2005) Nanowire-Based Programmable Architectures; ACM Journal on Emerging Technologies in Computing Systems (JETC); Vol. 1; No. 2; 109-162; 10.1145/1084748.1084750
• DeHon, André and Naeimi, Helia (2005) Seven strategies for tolerating highly defective fabrication; IEEE Design and Test of Computers; Vol. 22; No. 4; 306-315; 10.1109/MDT.2005.94
• DeHon, André and Goldstein, Seth Copen, el al. (2005) Nonphotolithographic nanoscale memory density prospects; IEEE Transactions on Nanotechnology; Vol. 4; No. 2; 215-228; 10.1109/TNANO.2004.837849
• DeHon, André (2004) Unifying mesh- and tree-based programmable interconnect; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 12; No. 10; 1051-1065; 10.1109/TVLSI.2004.834237
• DeHon, André and Rubin, Raphael (2004) Design of FPGA interconnect for multilevel metallization; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 12; No. 10; 1038-1050; 10.1109/TVLSI.2004.827562
• Kapre, Nachiket and Walther, Dirk B., el al. (2004) Saliency on a chip: a digital approach with an FPGA; The Neuromorphic Engineer; Vol. 1; No. 2; 9-11
• DeHon, André and Lincoln, Patrick, el al. (2003) Stochastic assembly of sublithographic nanoscale interfaces; IEEE Transactions on Nanotechnology; Vol. 2; No. 3; 165-174; 10.1109/TNANO.2003.816658
• DeHon, André (2003) Array-based architecture for FET-based, nanoscale electronics; IEEE Transactions on Nanotechnology; Vol. 2; No. 1; 23-32; 10.1109/TNANO.2003.808508
• DeHon, André (2000) The density advantage of configurable computing; Computer; Vol. 33; No. 4; 41-49; 10.1109/2.839320
• Mangione-Smith, William H. and Hutchings, Brad, el al. (1997) Seeking solutions in configurable computing; Computer; Vol. 30; No. 12; 38-43; 10.1109/2.642810