<h1>DeHon, Andre</h1>
<h2>Article from <a href="https://authors.library.caltech.edu">CaltechAUTHORS</a></h2>
<ul>
<li>Gojman, Benjamin and Nalmela, Sirisha, el al. (2014) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20150121-071331821">GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction</a>; ACM Transactions on Reconfigurable Technology Systems; Vol. 7; No. 4; Art. No. 32; <a href="https://doi.org/10.1145/2597889">10.1145/2597889</a></li>
<li>Naeimi, Helia and DeHon, André (2009) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20090831-143856470">Fault Secure Encoder and Decoder for NanoMemory Applications</a>; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 17; No. 4; 473-486; <a href="https://doi.org/10.1109/TVLSI.2008.2009217">10.1109/TVLSI.2008.2009217</a></li>
<li>Papadantonakis, Karl and Kapre, Nachiket, el al. (2009) <a href="https://resolver.caltech.edu/CaltechAUTHORS:PAPieeetc09">Pipelining Saturated Accumulation</a>; IEEE Transactions on Computers; Vol. 58; No. 2; 208-219; <a href="https://doi.org/10.1109/TC.2008.110">10.1109/TC.2008.110</a></li>
<li>Naeimi, Helia and DeHon, André (2008) <a href="https://resolver.caltech.edu/CaltechAUTHORS:NAEnanot08">Fault-tolerant sub-lithographic design with rollback recovery</a>; Nanotechnology; Vol. 19; No. 11; 115708; <a href="https://doi.org/10.1088/0957-4484/19/11/115708">10.1088/0957-4484/19/11/115708</a></li>
<li>Savage, John E. and Rachlin, Eric, el al. (2006) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20161213-174431809">Radial addressing of nanowires</a>; ACM Journal on Emerging Technologies in Computing Systems (JETC); Vol. 2; No. 2; 129-154; <a href="https://doi.org/10.1145/1148015.1148018">10.1145/1148015.1148018</a></li>
<li>DeHon, André (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05b">Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches</a>; IEEE Transactions on Nanotechnology; Vol. 4; No. 6; 681-687; <a href="https://doi.org/10.1109/TNANO.2005.858587">10.1109/TNANO.2005.858587</a></li>
<li>Dehon, André (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20160420-100045980">Nanowire-Based Programmable Architectures</a>; ACM Journal on Emerging Technologies in Computing Systems (JETC); Vol. 1; No. 2; 109-162; <a href="https://doi.org/10.1145/1084748.1084750">10.1145/1084748.1084750</a></li>
<li>DeHon, André and Naeimi, Helia (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeedtc05">Seven strategies for tolerating highly defective fabrication</a>; IEEE Design and Test of Computers; Vol. 22; No. 4; 306-315; <a href="https://doi.org/10.1109/MDT.2005.94">10.1109/MDT.2005.94</a></li>
<li>DeHon, André and Goldstein, Seth Copen, el al. (2005) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05a">Nonphotolithographic nanoscale memory density prospects</a>; IEEE Transactions on Nanotechnology; Vol. 4; No. 2; 215-228; <a href="https://doi.org/10.1109/TNANO.2004.837849">10.1109/TNANO.2004.837849</a></li>
<li>DeHon, André and Rubin, Raphael (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04a">Design of FPGA interconnect for multilevel metallization</a>; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 12; No. 10; 1038-1050; <a href="https://doi.org/10.1109/TVLSI.2004.827562">10.1109/TVLSI.2004.827562</a></li>
<li>DeHon, André (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04b">Unifying mesh- and tree-based programmable interconnect</a>; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Vol. 12; No. 10; 1051-1065; <a href="https://doi.org/10.1109/TVLSI.2004.834237">10.1109/TVLSI.2004.834237</a></li>
<li>Kapre, Nachiket and Walther, Dirk B., el al. (2004) <a href="https://resolver.caltech.edu/CaltechAUTHORS:20130816-103300863">Saliency on a chip: a digital approach with an FPGA</a>; The Neuromorphic Engineer; Vol. 1; No. 2; 9-11</li>
<li>DeHon, André and Lincoln, Patrick, el al. (2003) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03b">Stochastic assembly of sublithographic nanoscale interfaces</a>; IEEE Transactions on Nanotechnology; Vol. 2; No. 3; 165-174; <a href="https://doi.org/10.1109/TNANO.2003.816658">10.1109/TNANO.2003.816658</a></li>
<li>DeHon, André (2003) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn03a">Array-based architecture for FET-based, nanoscale electronics</a>; IEEE Transactions on Nanotechnology; Vol. 2; No. 1; 23-32; <a href="https://doi.org/10.1109/TNANO.2003.808508">10.1109/TNANO.2003.808508</a></li>
<li>DeHon, André (2000) <a href="https://resolver.caltech.edu/CaltechAUTHORS:DEHcomputer00">The density advantage of configurable computing</a>; Computer; Vol. 33; No. 4; 41-49; <a href="https://doi.org/10.1109/2.839320">10.1109/2.839320</a></li>
<li>Mangione-Smith, William H. and Hutchings, Brad, el al. (1997) <a href="https://resolver.caltech.edu/CaltechAUTHORS:MANcompute97">Seeking solutions in configurable computing</a>; Computer; Vol. 30; No. 12; 38-43; <a href="https://doi.org/10.1109/2.642810">10.1109/2.642810</a></li>
</ul>