[
    {
        "id": "thesis:2835",
        "collection": "thesis",
        "collection_id": "2835",
        "cite_using_url": "https://resolver.caltech.edu/CaltechETD:etd-07092007-072640",
        "primary_object_url": {
            "basename": "Burns_sm_1991.pdf",
            "content": "final",
            "filesize": 6219416,
            "license": "other",
            "mime_type": "application/pdf",
            "url": "/2835/1/Burns_sm_1991.pdf",
            "version": "v3.0.0"
        },
        "type": "thesis",
        "title": "Performance analysis and optimization of asynchronous circuits",
        "author": [
            {
                "family_name": "Burns",
                "given_name": "Steven Morgan",
                "clpid": "Burns-Steven-Morgan"
            }
        ],
        "thesis_advisor": [
            {
                "family_name": "Martin",
                "given_name": "Alain J.",
                "clpid": "Martin-A-J"
            }
        ],
        "thesis_committee": [
            {
                "family_name": "Martin",
                "given_name": "Alain J.",
                "clpid": "Martin-A-J"
            },
            {
                "family_name": "Seitz",
                "given_name": "Charles L.",
                "clpid": "Seitz-C-L"
            },
            {
                "family_name": "Van de Snepscheut",
                "given_name": "Jan L. A.",
                "clpid": "Van-de-Snepscheut-J-L-A"
            },
            {
                "family_name": "Franklin",
                "given_name": "Joel N.",
                "clpid": "Franklin-J-N"
            },
            {
                "family_name": "Chandy",
                "given_name": "K. Mani",
                "clpid": "Chandy-K-M"
            }
        ],
        "local_group": [
            {
                "literal": "div_eng"
            }
        ],
        "abstract": "Analytical techniques are developed to determine the performance of asynchronous digital circuits. These techniques can be used to guide the designer during the synthesis of such a circuit, leading to a high-performance, efficient implementation. Optimization techniques are also developed that further improve this implementation by determining the optimal sizes of the low-level devices (CMOS transistors) that compose the circuit.\r\n",
        "doi": "10.7907/kez1-7q52",
        "publication_date": "1991",
        "thesis_type": "phd",
        "thesis_year": "1991"
    },
    {
        "id": "thesis:6872",
        "collection": "thesis",
        "collection_id": "6872",
        "cite_using_url": "https://resolver.caltech.edu/CaltechTHESIS:03272012-085559361",
        "primary_object_url": {
            "basename": "Burns_sm_1987.pdf",
            "content": "final",
            "filesize": 2700129,
            "license": "other",
            "mime_type": "application/pdf",
            "url": "/6872/1/Burns_sm_1987.pdf",
            "version": "v5.0.0"
        },
        "type": "thesis",
        "title": "Automated Compilation of Concurrent Programs into Self-Timed Circuits",
        "author": [
            {
                "family_name": "Burns",
                "given_name": "Steven Morgan",
                "clpid": "Burns-Steven-Morgan"
            }
        ],
        "thesis_advisor": [
            {
                "family_name": "Unknown",
                "given_name": "Unknown"
            }
        ],
        "thesis_committee": [
            {
                "family_name": "None",
                "given_name": "None"
            }
        ],
        "local_group": [
            {
                "literal": "Computer Science Technical Reports"
            },
            {
                "literal": "div_eng"
            }
        ],
        "abstract": "No abstract.",
        "doi": "10.7907/j438-dz84",
        "publication_date": "1987",
        "thesis_type": "masters",
        "thesis_year": "1987"
    }
]