<h1>Bryant, Randal E.</h1>
<h2>Monograph from <a href="https://data.caltech.edu">CaltechTHESIS committee</a></h2>
<ul>
<li>Dally, William James (1986) <a href="https://resolver.caltech.edu/CaltechETD:etd-03252008-140428">A VLSI Architecture for Concurrent Data Structures</a>; <a href="https://doi.org/10.7907/f8d5-x741">10.7907/f8d5-x741</a></li>
<li>Lin, Tzu-mu (1985) <a href="https://resolver.caltech.edu/CaltechETD:etd-04102008-105646">A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems</a>; <a href="https://doi.org/10.7907/41bh-7e43">10.7907/41bh-7e43</a></li>
<li>DeBenedictis, Erik Penn (1982) <a href="https://resolver.caltech.edu/CaltechETD:etd-09062006-111645">Techniques for Testing Integrated Circuits</a>; <a href="https://doi.org/10.7907/ZKWD-NR73">10.7907/ZKWD-NR73</a></li>
<li>Lang, Charles Richard, Jr. (1982) <a href="https://resolver.caltech.edu/CaltechETD:etd-09142006-085516">The Extension of Object-Oriented Languages to a Homogeneous, Concurrent Architecture</a>; <a href="https://doi.org/10.7907/9EVC-2X08">10.7907/9EVC-2X08</a></li>
</ul>