@other{https://resolver.caltech.edu/CaltechETD:etd-03252008-140428,
    title = "A VLSI Architecture for Concurrent Data Structures",
    url = "https://resolver.caltech.edu/CaltechETD:etd-03252008-140428",
    id = "record",
    doi = "10.7907/f8d5-x741"
}


@other{https://resolver.caltech.edu/CaltechETD:etd-04102008-105646,
    title = "A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems",
    url = "https://resolver.caltech.edu/CaltechETD:etd-04102008-105646",
    id = "record",
    doi = "10.7907/41bh-7e43"
}


@other{https://resolver.caltech.edu/CaltechETD:etd-09142006-085516,
    title = "The Extension of Object-Oriented Languages to a Homogeneous, Concurrent Architecture",
    url = "https://resolver.caltech.edu/CaltechETD:etd-09142006-085516",
    id = "record",
    doi = "10.7907/9EVC-2X08"
}


@other{https://resolver.caltech.edu/CaltechETD:etd-09062006-111645,
    title = "Techniques for Testing Integrated Circuits",
    url = "https://resolver.caltech.edu/CaltechETD:etd-09062006-111645",
    id = "record",
    doi = "10.7907/ZKWD-NR73"
}