Reed-Solomon codes are known to provide excellent error-correcting capabilities on many types of communication channels. Although efficient decoding algorithms have been known for over fifteen years, currently available decoder systems are large both in size and in power consumption. Such systems typically use a single, very fast, fully parallel finite-field multiplier in a sequential architecture. Thus, more processing time is required as the code redundancy increases. By using many arithmetic units on a single chip, it is possible to exploit the concurrency inherent in the decoding algorithms to attain performance levels previously possible only with large ECL systems.
\r\n\r\nAn investigation into the structure of binary extension fields reveals that the common arithmetic operations used in decoding can be implemented quite efficiently in a bit-serial fashion, using any of several bases over GF(2). Berlekamp's dual-basis multiplier is generalized to the product of two arbitrary field elements, and a necessary and sufficient condition is then derived for the existence of a self-dual basis. Efficient methods for bit-serial multiplicative inversion are also discussed, greatly reducing the complexity traditionally associated with this operation.
\r\n\r\nUsing these bit-serial techniques, several architectures for implementing each phase of the known Reed-Solomon decoding algorithms are presented and compared. Simple methods are presented to allow power-sum syndrome decoders to handle codes with a variety of block lengths and redundancies. Each approach comes within a factor of log n (where n is the block length of the code) of the recently derived asymptotic lower bounds for both time and area. Results from a student project to lay out a prototype decoder chip using the Berlekamp-Massey algorithm are also discussed. By utilizing the parallelism inherent in the key equation solution, these architectures can decode received words at a speed independent of the redundancy of the code.
" }, { "name": "Trawick, David James", "degree": "PhD", "year": "1983", "title": "Robust Sentence Analysis and Habitability", "advisor": "Thompson, Frederick B.", "url": "https://resolver.caltech.edu/CaltechETD:etd-11032005-154728", "creators": [ { "name": { "family": "Trawick", "given": "David James" }, "id": "Trawick-David-James", "display_name": "Trawick, David James" } ], "advisors": [ { "name": { "family": "Thompson", "given": "Frederick B." }, "id": "Thompson-F-B", "role": "advisor", "display_name": "Thompson, Frederick B." } ], "committee": [ { "name": { "family": "Thompson", "given": "Frederick B." }, "id": "Thompson-F-B", "role": "chair", "display_name": "Thompson, Frederick B." }, { "name": { "family": "Kajiya", "given": "James Thomas" }, "id": "Kajiya-J-T", "role": "member", "display_name": "Kajiya, James Thomas" }, { "name": { "family": "Mead", "given": "Carver" }, "id": "Mead-C-A", "orcid": "0000-0003-4051-0462", "role": "member", "display_name": "Mead, Carver" }, { "name": { "family": "Thompson", "given": "Bozena H." }, "id": "Thompson-B-H", "role": "member", "display_name": "Thompson, Bozena H." }, { "name": { "family": "Tschoegl", "given": "Nicholas W." }, "id": "Tschoegl-N-W", "role": "member", "display_name": "Tschoegl, Nicholas W." } ], "option_major": [ "compsci" ], "doi": "10.7907/re17-h091", "abstract": "Systems for using subsets of English with computers have progressed much in the area of linguistic coverage of well-formed sentences for a specific task. Some methods have also been devised for the treatment of input that is almost well-formed. Nevertheless, it is still quite easy to stray over the bounds imposed by current natural language systems. Without proper diagnosis, this leads to interactive systems that are not habitable, i.e., systems that are not pleasant to use because they are not able to perform up to the user's expectations.
\r\n\r\nThis thesis presents an overall system for the treatment of several areas normally outside the limit of natural language systems, and for the diagnosis of any input. The system, Robust Sentence Analysis, includes procedures for handling ambiguous input, resolving input with anaphors (e.g. pronouns), making several kinds of major and minor corrections to input, and the interaction of all of these areas. The system does not treat every aspect of these methods of human interaction, but does provide for the more prevalent forms as found in simulations of user interaction in several modes: face-to-face, terminal-to-terminal, and human-to-computer (using a previously implemented natural language system). Thus the system incorporates the most likely forms found in human performance. Diagnostics are designed to lead the user back into the boundaries of the system.
\r\n\r\nThe Robust Sentence Analysis system is implemented as a part of the ASK System, A Simple Knowledgeable System.
" }, { "name": "Lang, Charles Richard, Jr.", "degree": "PhD", "year": "1982", "title": "The Extension of Object-Oriented Languages to a Homogeneous, Concurrent Architecture", "advisor": "Seitz, Charles L.", "url": "https://resolver.caltech.edu/CaltechETD:etd-09142006-085516", "creators": [ { "name": { "family": "Lang", "given": "Charles Richard, Jr." }, "id": "Lang-Charles-Richard", "display_name": "Lang, Charles Richard, Jr." } ], "advisors": [ { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "advisor", "display_name": "Seitz, Charles L." } ], "committee": [ { "name": { "family": "Bryant", "given": "Randy" }, "id": "Bryant-R", "role": "chair", "display_name": "Bryant, Randy" }, { "name": { "family": "Fox", "given": "Geoffrey C." }, "id": "Fox-G-C", "role": "member", "display_name": "Fox, Geoffrey C." }, { "name": { "family": "Johnsson", "given": "S. Lennart" }, "id": "Johnsson-S-Lennart", "role": "member", "display_name": "Johnsson, S. Lennart" }, { "name": { "family": "Kajiya", "given": "James Thomas" }, "id": "Kajiya-J-T", "role": "member", "display_name": "Kajiya, James Thomas" }, { "name": { "family": "Martin", "given": "Alain J." }, "id": "Martin-A-J", "role": "member", "display_name": "Martin, Alain J." }, { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "member", "display_name": "Seitz, Charles L." } ], "option_major": [ "compsci" ], "doi": "10.7907/9EVC-2X08", "abstract": "A homogeneous machine architecture, consisting of a regular interconnection of many identical elements, exploits the economic benefits of VLSI technology. A concurrent programming model is presented that is related to object oriented languages such as Simula and Smalltalk. Techniques are developed which permit the execution of general purpose object oriented programs on a homogeneous machine. Both the hardware architecture and the supporting software algorithms are demonstrated to scale their performance with the size of the system.
\r\n\r\nThe program objects communicate by passing messages. Objects may move about in the system and may have an arbitrary pointer topology. A distributed, on-the-fly garbage collection algorithm is presented which operates by message passing. Simulation of the algorithm demonstrates its ability to collect obsolete objects over the entire machine with acceptable overhead costs. Algorithms for maintaining the locality of object references and for implementing a virtual object capability are also presented.
\r\n\r\nTo insure the absence of hardware bottlenecks, a number of interconnection strategies are discussed and simulated for use in a homogeneous machine. Of those considered, the Boolean N-cube connection is demonstrated to provide the necessary characteristics.
\r\n\r\nThe object oriented machine will provide increased performance as its size is increased. It can execute a general purpose, concurrent, object oriented language where the size of the machine and its interconnection topology are transparent to the programmer.
" }, { "name": "Johannsen, David Lawrence", "degree": "PhD", "year": "1981", "title": "Silicon Compilation", "advisor": "Mead, Carver", "url": "https://resolver.caltech.edu/CaltechETD:etd-11092006-140405", "creators": [ { "name": { "family": "Johannsen", "given": "David Lawrence" }, "id": "Johannsen-David-Lawrence", "display_name": "Johannsen, David Lawrence" } ], "advisors": [ { "name": { "family": "Mead", "given": "Carver" }, "id": "Mead-C-A", "orcid": "0000-0003-4051-0462", "role": "advisor", "display_name": "Mead, Carver" } ], "committee": [ { "name": { "family": "Mead", "given": "Carver" }, "id": "Mead-C-A", "orcid": "0000-0003-4051-0462", "role": "chair", "display_name": "Mead, Carver" }, { "name": { "family": "Thompson", "given": "Frederick B." }, "id": "Thompson-F-B", "role": "co-chair", "display_name": "Thompson, Frederick B." }, { "name": { "family": "Kajiya", "given": "James Thomas" }, "id": "Kajiya-J-T", "role": "member", "display_name": "Kajiya, James Thomas" }, { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "member", "display_name": "Seitz, Charles L." }, { "name": { "family": "Ray", "given": "Charles B." }, "id": "Ray-Charles-B", "role": "member", "display_name": "Ray, Charles B." } ], "option_major": [ "compsci" ], "doi": "10.7907/32ha-8453", "abstract": "Modern integrated circuits are among the most complex systems designed by man. Although we have seen a rapid increase in fabrication technology, traditional design methodologies have not evolved at a rate commensurate with the increasing design complexity potential. These circuit design methodologies fail when applied to Very Large Scale Integrated (VLSI) circuit design. This thesis proposes a new design methodology which manages the complexity VLSI design, allowing economical generation of correctly functioning circuits.
\r\n\r\nCost is one measurement of a design methodology's value. A good design methodology rapidly and efficiently translates high level system specifications into working parts. Traditional techniques partition the translation process into many steps; each design tool is focused upon one of these design steps. This partitioning precludes the consideration of global constraints, and introduces a literal explosion of data being transfered between design steps. The design process becomes error-prone and time consuming.
\r\n\r\nThe technique of silicon compilation presented in this thesis automatically translates from high level specifications into correct geometric descriptions. In this approach, the designer interacts at a high level of abstraction, and need not be concerned with lower levels of detail, facilitating exploration of alternate system architectures. Furthermore, since the implementation is algorithmically generated, chip descriptions can be made correct by construction. Finally, the user is given technology independence, because the high level specification need not require knowledge of fabrication details. This flexibility allows the user to take advantage of technology advances.
\r\n\r\nThis thesis explores various aspects of silicon compilation, and presents a prototype compiler, Bristle Blocks. The methodology is demonstrated through the design of several chips. The practicality of the methodology results from the concern for efficiency of the design process and of the chip designs produced by the system.
" }, { "name": "Barton, Anthony Francis", "degree": "PhD", "year": "1980", "title": "A Fault Tolerant Integrated Circuit Memory", "advisor": "Seitz, Charles L.", "url": "https://resolver.caltech.edu/CaltechTHESIS:03212012-110600634", "creators": [ { "name": { "family": "Barton", "given": "Anthony Francis" }, "id": "Barton-Anthony-Francis", "display_name": "Barton, Anthony Francis" } ], "advisors": [ { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "advisor", "display_name": "Seitz, Charles L." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/dr7k-qn11", "abstract": "Most commercially produced integrated circuits are incapable of\r\ntolerating manufacturing defects. The area and function of the\r\ncircuits is thus limited by the probability of faults occurring\r\nwithin the circuit. This thesis examines techniques for using\r\nredundancy in memory circuits to provide fault tolerance and to\r\nincrease storage capacity.
\r\n\r\nA hierarchical memory architecture using multiple Hamming codes\r\nis introduced and analysed to determine its resistance to\r\nmanufacturing defects. The results of the analysis indicate that\r\nsubstantial yield improvement is possible with relatively modest\r\nincreases in circuit area. Also, the architecture makes it possible\r\nto build larger memory circuits than is economically feasible\r\nwithout redundancy.
" }, { "name": "Browning, Sally Anne", "degree": "PhD", "year": "1980", "title": "The Tree Machine: A Highly Concurrent Computing Environment", "advisor": "Mead, Carver", "url": "https://resolver.caltech.edu/CaltechETD:etd-12082006-153626", "creators": [ { "name": { "family": "Browning", "given": "Sally Anne" }, "id": "Browning-Sally-Anne", "display_name": "Browning, Sally Anne" } ], "advisors": [ { "name": { "family": "Mead", "given": "Carver" }, "id": "Mead-C-A", "orcid": "0000-0003-4051-0462", "role": "advisor", "display_name": "Mead, Carver" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/15zs-9x82", "abstract": "An architecture for a VLSI multiprocessor machine is proposed. The processors are connected together as a binary tree. A collection of algorithms are mapped onto the tree machine. These include heap sort transitive closure, the travelling salesman, and matrix inversion, among others. A model of computational complexity for the tree machine is suggested, and the algorithms are analyzed in the context of that model. A notation for expressing the algorithms is described, a processor design is proposed, and a compiler for the notation and processor is presented." }, { "name": "Hess, Gideon David", "degree": "PhD", "year": "1980", "title": "A Software Design System", "advisor": "Thompson, Frederick B.", "url": "https://resolver.caltech.edu/CaltechETD:etd-10182006-082833", "creators": [ { "name": { "family": "Hess", "given": "Gideon David" }, "id": "Hess-Gideon-David", "display_name": "Hess, Gideon David" } ], "advisors": [ { "name": { "family": "Thompson", "given": "Frederick B." }, "id": "Thompson-F-B", "role": "advisor", "display_name": "Thompson, Frederick B." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/Z9348HB7", "abstract": "The goal of the research described in this thesis was to build a system that supports, without interfering with, the activity of systematic software design and takes upon itself mechanical activities the designer can be spared.
\r\n\r\nTwo of the main activities which constitute the process of software creation are:
\r\n1.Designing a solution to the problem.
\r\n2. Implementing the design.
The activity of design has to be performed by the programmer himself, it can only be aided by the computer. Producing a program from a complete design is a mechanical activity the computer can take upon itself.
\r\n\r\nThese observations lead to the following objectives that a software design system should meet:
\r\n1. Providing tools that support the design activity and enable maximum flexibility.
\r\n2. Recognizing the lowest level primitives of the design as the target language and producing the program in this language.
A system along these guidelines was implemented. It permits the user to write definitions which refine high level design decisions into lower levels and, at the same time, serve as syntax descriptions and translation rules for the languages used in the design.
\r\n\r\nThe system operates in two user-controlled passes. In the first pass the user's definitions are read, either interactively or from external files, and the syntax rules are stored in a dictionary. In the second pass a syntax driven language processor uses the dictionary to compile the user's program into the target language which consists of the lowest level constructs of the design.
\r\n\r\nDue to the freedom the programmer has in design, several kinds of syntactic ambiguities may be introduced with - or without - the user's attention. Unless caused by user errors, the translator tries to resolve these ambiguities to match the designers intentions.
\r\n\r\nIn order to reduce the amount of time and space required for parsing, long texts are divided into subtexts which are translated separately. Guidance as to which subtexts are separately translatable is provided by the user in a natural way by composing the design of statements.
\r\n\r\nA command language enables the user to control the passes, to look at the contents of the dictionary and of external files, to monitor the translation process for debugging purposes, to store dictionaries for later use and retrieve them and to modify special symbols used in definitions.
\r\n\r\nThe system is implemented in Simula. A second system is presently being implemented as part of POL (Problem Oriented Language), a system for writing and using application languages. POL's metalanguage enables the user to build - or extend object languages by writing new syntax rules. The tools of the development system described above are incorporated into the metalanguage in order to aid the application programmer in the design and compilation of the semantic routines of these rules.
" }, { "name": "Rowson, James Allely", "degree": "PhD", "year": "1980", "title": "Understanding Hierarchical Design", "advisor": "Mead, Carver", "url": "https://resolver.caltech.edu/CaltechETD:etd-12062006-104710", "creators": [ { "name": { "family": "Rowson", "given": "James Allely" }, "id": "Rowson-James-Allely", "display_name": "Rowson, James Allely" } ], "advisors": [ { "name": { "family": "Mead", "given": "Carver" }, "id": "Mead-C-A", "orcid": "0000-0003-4051-0462", "role": "advisor", "display_name": "Mead, Carver" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/Z9BP00R2", "abstract": "With the exponential improvement in integrated circuit technology comes the problem of how to design systems containing millions of devices. This thesis presents a new look at hierarchical design based on the Caltech structured design methodology.\r\n\r\nThe hierarchy is separated into two parts: leaf cells, containing no instances of other cells, and composition cells, containing only instances of other cells. A leaf cell can be implemented in many different representations. A representation consists of a set of leaf cells and a composition rule that builds correct higher level cells.\r\n\r\nThe separated hierarchy is suitable for mathematical analysis by the use of Curry's theory of combinators. In this form, a hierarchy is represented by a mathematical operator that produces a digital system from the leaf cells. The question of hierarchical equivalence is examined.\r\n\r\nThree sample composition rules, or algorithms, are presented as examples. The SLAP system provides a geometry composition rule that produces the mask description of a system given the geometries of the leaf cells. In analogy to TYPEing in a programming language, two representations that enforce a certain design style are discussed. The first TYPE system guarantees signal integrity. The second TYPE system guarantees mutual exclusion between the sources on a bus." }, { "name": "Ayres, Ronald Frederick", "degree": "PhD", "year": "1979", "title": "A Language Processor and a Sample Language", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:10072021-184918786", "creators": [ { "name": { "family": "Ayres", "given": "Ronald Frederick" }, "id": "Ayres-Ronald-Frederick", "display_name": "Ayres, Ronald Frederick" } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/r2hy-6x63", "abstract": "This thesis explores shared data in list structures and ambiguity in language processing. Tolerance of ambiguity is necessary to support clear and modular expression. Data sharing is necessary to support ambiguity efficiently. Data sharing is useful also in compiled programs to save memory and time.
\r\n\r\nLet us define some terms. A rewrite grammar is a set of replacement rules each of which specifies that a given phrase may be replaced by another given phrase. Each replacement rule expresses a local translation. A parser finds those sequences of replacements that bring a given text to a machine handleable form. Each such sequence represents a meaning or interpretation for the given text. Tolerance of ambiguity or multiple interpretations for a given text is necessary so that subsequent processing can place further constraints upon the input text.
\r\n\r\nThis thesis presents a parser which efficiently, handles general-rewrite grammars. To conserve computer time and memory, only essential differences among multiple interpretations are represented and processed. If several interpretations for a given text are valid, the parser yields a meaning which represents the ambiguity as, locally as possible. Even an exponential number of distinct meanings may be represented in a polynomial amount of memory.
\r\n\r\nThis thesis also presents a language processing system which supports semantic processing via independent rewrite grammars. Each grammar represents a distinct aspect of the language. A given sequence of grammars becomes a sequence of passes, or process steps. Each pass derives a meaning with respect to one grammar and uses that meaning to generate phrases which will be interpreted by the next pass. Although linguistic specification is usually done with context-free grammars, features of this parser which support general-rewrite grammars are essential for the integration of passes. Not only ambiguity, but also the locality of ambiguity is preserved from one pass to the next. It is necessary to preserve\r\nlocality of ambiguity in order to avoid explosive computation arising from useless action among independent sets of interpretations.
\r\n\r\nI have implemented a general-purpose programming language called ICL with this system. The fact that ICL's datatypes are processed by a rewrite grammar makes it simple to implement both user-defined datatype coercions and functions known as polymorphic operators whose definitions depend on parameter datatypes. Datatype coercions and Polymorphic operators reduce the amount,of specification required in algorithms to such an extent that a user can often modify declarations and achieve optimizations and changes in concept without modifying his algorithmic specification.
\r\n\r\nICL includes a simple and safe policy about pointers so that the user can ignore their existence completely if he wishes. ICL automatically maximizes data sharing and minimizes copying by adopting a \"copy on write\" policy. This policy supports the illusion that each and every reference to a data structure generates a\r\ncomplete copy of that data structure. This same technique is used in the language processor itself to facilitate data sharing among multiple interpretations in ambiguous cases.
" } ]