This thesis is concerned with the interconnection problem of custom integrated circuits. It may be broadly defined as the transformation of circuit description represented by the notion of modules together with the circuit connectivity requirements, into wiring patterns which implement the required connectivities. Conventional approaches to its solution are presented. Issues such as partition to placement and routing and various layout optimization tradeoffs are discussed. A detail hierarchical routing model with timing considerations that extends naturally to multiple conducting layer environment is presented. Several of the implications of this extension are also discussed.
\r\n\r\nThe rest of this thesis deals with an experiment with the stepping approach to routing as an alternative to the conventional cellular approach emphasizing simplicity rather than optimization. Algorithms for routing signals and power developed for the stepping router are presented. An implementation of this approach by the author together with some test examples and their results are also described. This thesis concludes with a few suggestions for further research work in this area which the author considers very important from the experience gained during the work on this thesis.
" }, { "name": "Oyang, Yen-Jen", "degree": "Masters", "year": "1984", "title": "HEX: A Hierarchical Circuit Extractor", "advisor": "Bryant, Randal E.", "url": "https://resolver.caltech.edu/CaltechTHESIS:05022012-105611552", "creators": [ { "name": { "family": "Oyang", "given": "Yen-Jen" }, "id": "Oyang-Y-J", "orcid": "0009-0001-6241-9881", "display_name": "Oyang, Yen-Jen" } ], "advisors": [ { "name": { "family": "Bryant", "given": "Randal E." }, "id": "Bryant-R", "orcid": "0000-0001-5024-6613", "role": "advisor", "display_name": "Bryant, Randal E." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/mptd-b683", "abstract": "This report describes the algorithm, implementation, and performance of a hierarchical circuit extractor, HEX, for Metal-Oxide Semiconductor (MOS) layout designs at Caltech. The input to HEX is a layout design in Caltech\r\nIntermediate Form (CIF), a hierarchical layout description language, and the output is a hierarchical netlist describing the circuit. HEX avoids redundant\r\nwork by finding out the repetitive cells in the input CIF file. To handle overlapping instances, HEX modifies the hierarchy in the CIF file to generate a new one without overlapping instances. HEX then traverses the resulting\r\nhierarchical structure, calls a flat extractor to extract leaf cells and composes cells bottom up to get the circuit information of the whole chip." }, { "name": "Su, Wen-King", "degree": "Masters", "year": "1984", "title": "Supermesh", "advisor": "Seitz, Charles L.", "url": "https://resolver.caltech.edu/CaltechTHESIS:04122012-161148552", "creators": [ { "name": { "family": "Su", "given": "Wen-King" }, "id": "Su-Wen-King", "display_name": "Su, Wen-King" } ], "advisors": [ { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "advisor", "display_name": "Seitz, Charles L." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/yvj1-jt57", "abstract": "No abstract." }, { "name": "Athas, William C.", "degree": "Masters", "year": "1983", "title": "A VLSI Combinator Reduction Engine", "advisor": "Seitz, Charles L.", "url": "https://resolver.caltech.edu/CaltechTHESIS:03262012-092805759", "creators": [ { "name": { "family": "Athas", "given": "William C." }, "id": "Athas-William-C", "display_name": "Athas, William C." } ], "advisors": [ { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "advisor", "display_name": "Seitz, Charles L." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/r471-je71", "abstract": "No abstract." }, { "name": "Choo, Young-il", "degree": "Masters", "year": "1983", "title": "Hierarchical Nets: A Structured Petri Net Approach to Concurrency", "advisor": "Kajiya, James Thomas", "url": "https://resolver.caltech.edu/CaltechTHESIS:04022012-150759898", "creators": [ { "name": { "family": "Choo", "given": "Young-il" }, "id": "Choo-Young-il", "display_name": "Choo, Young-il" } ], "advisors": [ { "name": { "family": "Kajiya", "given": "James Thomas" }, "id": "Kajiya-J-T", "role": "advisor", "display_name": "Kajiya, James Thomas" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/t5w4-vt07", "abstract": "Liveness and safeness are two key properties Petri nets should have when they are used to model asynchronous systems. The analysis of liveness and safeness for general Petri nets, though shown to be decidable by Mayr [1981], is still computationally expensive (Lipton [1976]). In this paper an hierarchical approach is taken: a class of Petri nets is recursively defined starting with simple, live and safe structures, becoming progressively more complex using net transformations designed to preserve liveness and safeness.
\r\n\r\nUsing simple net transformations, nice nets, which are live and safe, are defined. Their behavior is too restrictive for modeling non-trivial systems, so the mutual exclusion and the repetition constructs are added to get \u00b5-\u03c1-nets. Since the use of mutual exclusions can cause deadlock, and the use of repetitions can cause loss of safeness, restrictions for their use are given. Using \u00b5-\u03c1-nets as the building blocks, hierarchical nets are defined. When the mutual exclusion and repetition constructs are allowed between hierarchical nets, distributed hierarchical nets are obtained. Examples of distributed hierarchical nets used to solve synchronization problems\r\nare given.
\r\n\r\nGeneral net transformations not preserving liveness or safeness, and a notion of duality are presented, and their effect on Petri net behavior is considered.
" }, { "name": "Holstege, Eric John", "degree": "Masters", "year": "1983", "title": "Type Inference in a Declarationless, Object-Oriented Language", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:04112012-080413185", "creators": [ { "name": { "family": "Holstege", "given": "Eric John" }, "id": "Holstege-Eric-John", "display_name": "Holstege, Eric John" } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/sa4t-bn94", "abstract": "In recent years, two developments in the design of programming languages have yielded significant improvements in a number of areas from the standard FBAPP programming model. These are the object-oriented paradigm, and variable polymorphism.
\r\n\r\nThe object-oriented programming model allows the specification, hence restriction of the operations allowed on a data structure, something not possible with the more traditional PASCAL-style record structuring. This\r\nability to encapsulate data from the outside world gives a greater security and error avoidance in very large software projects involving many programmers.
\r\n\r\nIn addition, the object-oriented style is conceptually easy to program in, providing a useful framework for the subdivision of large problems into manageable pieces. This property is essential for the rapid and reliable\r\nimplementation of large software systems.
\r\n\r\nVariable polymorphism refers to the ability of variables to change types at runtime. This is in contradistinction to typelessness (as in BLISS) where variables have no types associated with them. In most common languages,\r\nthe programmer must declare the types of all the variables he uses; these types are then static throughout the execution of the program. Declarations allow the compiler to produce efficient code and to identify errors whose\r\ndetection must other-wise be deferred until runtime; however, they sacrifices a good deal of the generality which is possible with less stringent variable\r\nbinding schemes. On the other hand, languages which don't require declarations, and which allow variables to change types, such as SNOBOL and LISP, provide this generality by virtue of their extremely late binding, but thereby sacrifice efficiency.
\r\n\r\nSMALLTALK is perhaps the purest language which embodies both object-orientedness and declarationlessness. Unfortunately, these two features, while of great benefit in increasing programmer productivity and program\r\nreliability, suffer heavily from the point of view of runtime efficiency.
\r\n\r\nThe project is to investigate ways to obtain the undeniable advantages of polymorphism and object-orientedness, without sacrificing runtime\r\nefficiency. More specifically, the goal is to build a compiler for a dialect of SMALLTALK for the VAX under UNIX (Berkeley 4.1bsd), which incorporates data-flow type inference algorithms enabling it to produce executable\r\nprograms of an efficiency comparable to that of programs produced by compilers for more traditional but less powerful languages.
\r\n\r\nThe optimization methods are described, test results are examined, and indications of future directions are given.
" }, { "name": "Lam, Jimmy Kwok-Ching", "degree": "Masters", "year": "1983", "title": "RTsim: A Register Transfer Simulator", "advisor": "Bryant, Randal E.", "url": "https://resolver.caltech.edu/CaltechTHESIS:04112012-091046970", "creators": [ { "name": { "family": "Lam", "given": "Jimmy Kwok-Ching" }, "id": "Lam-Jimmy-Kwok-Ching", "display_name": "Lam, Jimmy Kwok-Ching" } ], "advisors": [ { "name": { "family": "Bryant", "given": "Randal E." }, "id": "Bryant-R", "role": "advisor", "display_name": "Bryant, Randal E." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/727m-mf30", "abstract": "The growing complexity and size of VLSI processors are demanding extremely accurate, simulation facilities for microcode debugging, logic verification, and system integration. However, reliance on mask iterations to remedy problems on a chip not only raises costs, but also extends the design cycle. Simulation justifies itself in both the turn around time and the design cost. Gate level simulation is one method for reducing errors in a chip design. However, gate level simulation of large designs are extremely expensive, and sometimes impossible when the gate level representation is not known. This thesis attempts to solve this problem by providing a functional modeling language, a reconfigurable assembler, and a functional simulation program. Mixed-level simulation capability is also provided by allowing the replacement of a functional unit by a transistor network which is being simulated by a switch-level logic simulator." }, { "name": "Ng, Charles Hok-Bun", "degree": "Masters", "year": "1983", "title": "FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems", "advisor": "Seitz, Charles L.", "url": "https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723", "creators": [ { "name": { "family": "Ng", "given": "Charles Hok-Bun" }, "id": "Ng-Charles-Hok-Bun", "display_name": "Ng, Charles Hok-Bun" } ], "advisors": [ { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "advisor", "display_name": "Seitz, Charles L." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/vdzd-7h35", "abstract": "This thesis describes a family of VLSI chips designed to link a number of processors on a one-to-one basis. With these chips as communication system building blocks, a complex multiprocessor system can be built. Inter-processor communication within the multiprocessor system is accomplished by passing messages composed of data packets.
\r\n\r\nThe resulting chip, called a First-in-first-out Buffering Transceiver (FIBT), provides a full duplex communication channel between any two processors. FIFO queues are provided for buffering data on each communication channel. FIBT accepts data packets from the host processor via a parallel data bus and serially sends them out to the destined processor. FIBT handshakes with the processor by using asynchronous interrupt signals.
\r\n\r\nLinkage between any two FIBTs is accomplished by using only two wires. Both data bits and handshaking signals are sent by these two lines. The FIBT system is neither a synchronous nor an asynchronous one; instead, it is an \"one-clock-different-phases\" system. A clock signal sets up the frequency reference; the start and stop bits set up the phase reference.
\r\n\r\nFinally, FIBT is implemented in nMOS technology. The design of the circuit is discussed in detail. The design is generalized enough so that data packets of various sizes can be handled. The layout of the chip is coded in an integrated circuit descriptive language. Any member of the family of chips can be obtained by changing three basic parameters. Techniques used in verifying the circuit are shown, and several observations about VLSI design are offered.
" }, { "name": "Kingsley, Christopher Hayden", "degree": "Masters", "year": "1982", "title": "EARL: An Integrated Circuit Design Language", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:04112012-082810035", "creators": [ { "name": { "family": "Kingsley", "given": "Christopher Hayden" }, "id": "Kingsley-Christopher-Hayden", "display_name": "Kingsley, Christopher Hayden" } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/z452-0r86", "abstract": "No abstract." }, { "name": "Whiting, Douglas Lee", "degree": "Masters", "year": "1982", "title": "A Self-Timed Chip Set for Microprocessor Communication", "advisor": "Seitz, Charles L.", "url": "https://resolver.caltech.edu/CaltechTHESIS:04122012-110450092", "creators": [ { "name": { "family": "Whiting", "given": "Douglas Lee" }, "id": "Whiting-Douglas-Lee", "display_name": "Whiting, Douglas Lee" } ], "advisors": [ { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "advisor", "display_name": "Seitz, Charles L." } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/tnv1-t713", "abstract": "This paper describes a family of chips used to link multiple processors together on a speed-independent communication bus. Sendership arbitration is included as an integral part of the signalling scheme, incurring very little overhead and providing a measure of fairness. The protocol allows for one-to-many communication in which the sender must wait for all receivers to respond to each datum transmitted. The width of the data bus is arbitrary, and only three control wires are necessary for normal transmission cycles. In order to alleviate congestion, the global bus may be divided into several local buses by a method which is entirely transparent to the processor software. Thus the bus topology may be reconfigured for each processing network using these chips as building blocks.
\r\n\r\nFunctional verification of speed-independent circuits is also discussed. The problem is seen to be very complex, but some conclusions are drawn about the type of tools which will be helpful in implementing self-timed systems.
" }, { "name": "Gray, Moshe", "degree": "Masters", "year": "1981", "title": "The Design and Implementation of a Reticle Maker for VLSI", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:03122018-162127158", "creators": [ { "name": { "family": "Gray", "given": "Moshe" }, "id": "Gray-Moshe", "display_name": "Gray, Moshe" } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "None", "given": "None" }, "display_name": "None, None" } ], "option_major": [ "compsci" ], "doi": "10.7907/0v5p-7011", "abstract": "This paper describes the designing and building of a feedback controlled Reticle Maker for the VLSI industry. The machine is based on an innovative design of an XY photo plotter which utilizes flexures and linear motors as a means to raster scan a photographic plate. The accuracy of the machine is based on Laser Interferometery and feedback control. " }, { "name": "Lien, Sheue-Ling C.", "degree": "Masters", "year": "1981", "title": "Toward a Theorem Proving Architecture", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:04122012-090812718", "creators": [ { "name": { "family": "Lien", "given": "Sheue-Ling C." }, "id": "Lien-Sheue-Ling-C", "display_name": "Lien, Sheue-Ling C." } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/ctky-sp95", "abstract": "No abstract." }, { "name": "Lin, Tzu-Mu", "degree": "Masters", "year": "1981", "title": "From Geometry to Logic", "advisor": "Mead, Carver", "url": "https://resolver.caltech.edu/CaltechTHESIS:04122012-091736952", "creators": [ { "name": { "family": "Lin", "given": "Tzu-Mu" }, "id": "Lin-Tzu-Mu", "display_name": "Lin, Tzu-Mu" } ], "advisors": [ { "name": { "family": "Mead", "given": "Carver" }, "id": "Mead-C-A", "orcid": "0000-0003-4051-0462", "role": "advisor", "display_name": "Mead, Carver" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/887g-zn84", "abstract": "Transformation between five different intermediate forms used in VLSI design are discussed. The intermediate forms are: the D language, Akers' Diagrams, transistor listings, the sticks standard, and CIF language. They represent architecture, logic, transistor, topology and geometric levels, respectively. To understand more about the relationships between these levels, a series of transformations from the CIF to the sticks standard, from the sticks standard to the transistor listing, and from the transistor listing to the Akers' Diagram are presented. By doing this, the description gap between the logical world and the physical world is bridged.
\r\n\r\nCAD developers often complain about the lack of a model that can be applied uniformly throughout the entire design process. Akers' Diagrams seem to meet this demand. This work highlights this point.
\r\n\r\nAs an example, a shift register implemented in NMOS technology will appear many times in this thesis.
" }, { "name": "Mosteller, Richard Craig", "degree": "Masters", "year": "1981", "title": "REST: A Leaf Cell Design System", "advisor": "Kajiya, James Thomas", "url": "https://resolver.caltech.edu/CaltechTHESIS:04122012-162654185", "creators": [ { "name": { "family": "Mosteller", "given": "Richard Craig" }, "id": "Mosteller-Richard-Craig", "display_name": "Mosteller, Richard Craig" } ], "advisors": [ { "name": { "family": "Kajiya", "given": "James Thomas" }, "id": "Kajiya-J-T", "role": "advisor", "display_name": "Kajiya, James Thomas" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/1r9d-ad60", "abstract": "This thesis describes a leaf cell design system, REST, Richard's Editor for Sticks. REST is intended to be used for the preparation of the lowest level cells in an integrated circuit design. A stick notation is used in the editing process. Given a structured design methodology any design task can be separated into two parts: 1) leaf cell design and 2) composition cell design. This tool addresses the first of these tasks, although it may also be used for general manipulation of stick diagrams. A table driven compaction algorithm is presented. This graph based algorithm uses a weighted affinity factor to reduce total polysilicon and diffusion wire length. A suite of utilities provide functions such as file interface, physical mapping, annotation, etc. consistent with a set of design rules. The system has been implemented in Simula on a DEC 20 computer, and works in conjunction with a limited functional diagramming system. The design rules, models and stick interpretation are table driven and can be changed for various technologies. Currently REST is being used for NMOS technology. A community of users have used the REST system to prepare a number of designs resulting in a substantial reduction of design time. In addition, the system is currently being used at a major computer manufacturer in conjunction with a VLSI design course." }, { "name": "S\u00e9gal, Richard Lawrence", "degree": "Masters", "year": "1981", "title": "Structure, Placement and Modelling", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:04132012-091556662", "creators": [ { "name": { "family": "S\u00e9gal", "given": "Richard Lawrence" }, "id": "S\u00e9gal-Richard-Lawrence", "display_name": "S\u00e9gal, Richard Lawrence" } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/tb24-mg70", "abstract": "The nature of hierarchical design tools for VLSI implementation is explored in\r\nterms of the \"Caltech Structured Design Philosophy\" as interpreted by Rowson in his\r\ndoctoral thesis [Rowson]. One obvious implication of this thesis is the desirability\r\nof tools for leaf and composition cell design. This thesis describes one such tool\r\ntargeted at the composition cell design problem. It is intended to be used in the\r\narchitectual phases of a design and allows structural (interface specification),\r\nphysical (floor planing), and behavioral (simulation modelling) descriptions to be\r\nwritten down, integrated, and tested. One biproduct of this process is the\r\ngeneration or a comprehensive design document from which workbooks can be\r\ngenerated automatically.
\r\n\r\nThe later sections describe a hierarchical simulator and how it fits into the\r\nstep-wise refinement process of design. The most important considerations in the\r\ndesign of this simulator were ease of expression and the provision of enough\r\ngenerality to allow the specification of any VLSI structure. Simulation takes place\r\nin a time axis/delay environment and uses a system in which nodes may take one of\r\nfour values or states. This allows a high level simulation in which physical devices\r\nare replaced by register transfer type operations. Data is altered and moved around\r\nusing flow control mechanisms, logical and mathematical operations, and various\r\nmeans of specifying delay. Though not necessary or typical it is possible to model\r\nactual devices as ideal switches using these techniques. It is a multi-model\r\nsimulation because simulation can occur at any level or design abstraction. Several\r\nexamples are given including the modelling or the GR2 stack data microprocessor\r\nwhich was recently fabricated in NMOS.
" }, { "name": "Whelan, Daniel Steven", "degree": "Masters", "year": "1981", "title": "A Versatile Ethernet Interface", "advisor": "Kajiya, James Thomas", "url": "https://resolver.caltech.edu/CaltechTHESIS:04122012-112531771", "creators": [ { "name": { "family": "Whelan", "given": "Daniel Steven" }, "id": "Whelan-Daniel-Steven", "display_name": "Whelan, Daniel Steven" } ], "advisors": [ { "name": { "family": "Kajiya", "given": "James Thomas" }, "id": "Kajiya-J-T", "role": "advisor", "display_name": "Kajiya, James Thomas" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/x4t9-5n88", "abstract": "No abstract." }, { "name": "Whitney, Telle", "degree": "Masters", "year": "1981", "title": "A Hierarchical Design Rule Checker", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:04122012-100224959", "creators": [ { "name": { "family": "Whitney", "given": "Telle" }, "id": "Whitney-T", "display_name": "Whitney, Telle" } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/dqz1-c122", "abstract": "This thesis describes a new approach to the problem of Geometrical Design Rule Checking (DRC). Previous DRC implementations have dealt with fully instantiated geometrical artwork. As the complexity of VLSI increases, it becomes infeasible to analyze the vast amounts of information present in a fully instantiated design. The\r\nDRC algorithm presented here introduces an approach that exploits the structural\r\nhierarchy of a design in order to reduce the computational complexity of the\r\ngeometrical tests that need to be made. The technique described is also applicable to\r\nother types of design checking such as circuit extraction, functional verification\r\nand electrical rule verification.
\r\n\r\nA new DRC algorithm has been developed that, by making use of the structure\r\ninherent in a hierarchical design, eliminates many redundant design rule checks.\r\nIn this approach there are two places where possible design rule violations may\r\noccur. The first is within a symbol definition. The second is the area where two\r\nsymbols interact. The algorithm checks a given definition only once, and then examines how interactions within each new environment where the definition is placed modify the original definition. A note is made after each interaction has been scrutinized, so that a duplicate situation will not be rechecked.
\r\n\r\nAn implementation of the hierarchical DRC algorithm has been written at Caltech.\r\nThis implementation extracts a minimal number of pairwise geometrical\r\ncomparisons needed to check the entire design. The program accepts as in put a\r\ndesign description in the Caltech Intermediate Form (CIF). The output of the program is currently a fully instantiated version of those portions of the geometry\r\nthat need to be checked in order to check the entire design.
\r\n\r\nA means of expressing the designer's intent through the design description is\r\nrequired. Current DRC's deal with geometrical artwork exclusively. Most of the\r\ndifficult design rules are involved in the checking of devices. Rather than\r\nrestricting the designer to the use of geometry, the idea of a primitive element is\r\nintroduced. A primitive element is defined to be anything that cannot be broken\r\ndown into sub-elements. A design defined using primitive elements conveys more\r\nof the functional structure than a purely geometric definition.
\r\n\r\n" }, { "name": "Demetrescu, Stefan Gabriel", "degree": "Masters", "year": "1980", "title": "A VLSI Based Real-Time Hidden Surface Elimination Display System", "advisor": "Unknown, Unknown", "url": "https://resolver.caltech.edu/CaltechTHESIS:04092012-133954577", "creators": [ { "name": { "family": "Demetrescu", "given": "Stefan Gabriel" }, "id": "Demetrescu-Stefan-Gabriel", "display_name": "Demetrescu, Stefan Gabriel" } ], "advisors": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/Z9GF0RGD", "abstract": "This thesis describes a novel approach to the problem of generating dynamic TV raster displays for real-time simulation (such as for visual flight simulation). In particular, the most time consuming part of generating such displays, the hidden surface elimination, is performed using many identical custom VLSI processors. Each processor is assigned a surface and, for each pixel, all processors compete to decide which object is visible.
\r\n\r\nIt is found that this approach leads to a practical system which is conceptually and practically simple, expandible, and reliable.
" }, { "name": "Lang, Charles Richard", "degree": "Masters", "year": "1980", "title": "Automated Wiring Analysis of Integrated Circuit Geometric Data", "advisor": "Seitz, Charles L.", "url": "https://resolver.caltech.edu/CaltechThesis:03092018-151643742", "creators": [ { "name": { "family": "Lang", "given": "Charles Richard" }, "id": "Lang-Charles-Richard", "display_name": "Lang, Charles Richard" } ], "advisors": [ { "name": { "family": "Seitz", "given": "Charles L." }, "id": "Seitz-C-L", "role": "advisor", "display_name": "Seitz, Charles L." } ], "committee": [ { "name": { "family": "None", "given": "None" }, "display_name": "None, None" } ], "option_major": [ "compsci" ], "doi": "10.7907/qxbg-2c10", "abstract": "Methods are presented by which wiring data of an NMOS integrated circuit may be extracted from its mask information. The procedures involved utilize the capabilities of a general purpose polygon package. The polygon operations are defined to enhance their use in this application, however the package is suitable for other uses such as, design rule checking. The analysis is performed on hierarchical symbol definitions of mask geometry. The geometry is presumed to be described in CIF 2.0 (Caltech Intermediate Form). The analysis attempts to recognize three basic types of structures in the geometry:
\r\n\r\n1)\tTransistor devices (and capacitors)
\r\n2)\tLocal interconnection structures and
\r\n3)\tGlobal interconnection structures
Definitions are put forth for the distinction of global and local wires. The data extracted from the symbol geometry is the percent utilization of each symbol's area by each of the three types of structures. The purpose behind the extraction of this data is its use in the development and evaluation of wiring models for custom NMOS IC design. Two approaches are presented which extract such data. The first is heuristic and depends on built-in assumptions of how the NMOS process is generally used. This technique loses accuracy if a design style falls outside of these assumptions. The second technique is a method by which the topology of design may be extracted from the geometry. The geometric objects, from which devices and interconnections are made, are preserved, such that the wiring information can be obtained precisely. This method is complex and requires considerable computation, however, the topology extracted may also be used to verify the geometric data against the original design topology.
" }, { "name": "Seiler, Larry Dean", "degree": "Masters", "year": "1980", "title": "A Pascal Machine Architecture Implemented in Bristle Blocks, a Prototype Silicon Computer", "advisor": "Mudge, J. Craig", "url": "https://resolver.caltech.edu/CaltechTHESIS:03122018-143833053", "creators": [ { "name": { "family": "Seiler", "given": "Larry Dean" }, "id": "Seiler-Larry-Dean", "display_name": "Seiler, Larry Dean" } ], "advisors": [ { "name": { "family": "Mudge", "given": "J. Craig" }, "id": "Mudge-J-C", "role": "advisor", "display_name": "Mudge, J. Craig" } ], "committee": [ { "name": { "family": "Unknown", "given": "Unknown" }, "display_name": "Unknown, Unknown" } ], "option_major": [ "compsci" ], "doi": "10.7907/Z9VH5KTT", "abstract": "This thesis presents the multi-chip design of an architecture which directly implements the\r\nlanguage Pascal. The design uses custom VLSl rather than standard chips in order to\r\nincrease speed and reduce the number of chips needed.
\r\n\r\nThe integrated circuits comprising the architecture are designed using Bristle Blocks, a chip\r\ndesign tool developed at Caltech by Dave Johannsen (6). Bristle Blocks is called a silicon\r\ncompiler because it will put together an entire integrated circuit from a high level description\r\nof its function. Bristle Blocks can be used to design datapath processor chips, where\r\nexternal microcode is used to control operations on data busses inside the chip.
\r\n\r\nThe Pascal machine architecture presented here is based on the EM-1 instruction set\r\ndesigned by Andrew Tannenbaum (11,13). The EM-1 instruction set is intended to allow\r\nefficient compilation of stack-based, high level languages. Tannenbaum supplies static\r\nfrequency data which is used heavily in making design decisions in the Pascal machine\r\narchitecture.
\r\n\r\nVLSl design has several important differences from design using standard components. A\r\nlarge amount of function can be placed on a single chip, e.g., approximately 30,000\r\ntransistors on the Intel 8086, but only a small number of pins are available for off-chip\r\ncommunication (typically 64 or less). This requires designs to be highly modular. In the\r\nNMOS technology used at Caltech, driving signals off-chip takes up to ten times the time and\r\nenergy of on-chip communication. This requires inter-chip communication to be limited as\r\nmuch as possible. Finally, the large amount of computing power available in VLSl\r\nencourages the use of concurrency to gain execution speed.
\r\n\r\nThis thesis is structured as follows. The thesis begins with a section defining the principles\r\nto be followed in designing the Pascal system architecture. Following that are sections\r\ndescribing Bristle Blocks and the EM-1 architecture. Next, the overall architecture of the\r\nPascal machine is described, followed by sections detailing the system data busses, the\r\ncommon elements in the processors which make up the system, and the processors\r\nthemselves. A conclusion section summarizes the work, provides a brief critique of Bristle\r\nBlocks, and includes recommendations for further work. Finally, the appendices document\r\nthe Bristle Blocks datapath elements and the EM-1 instruction set.
" } ]