@other{https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723, title = "FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems", url = "https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723", id = "record", doi = "10.7907/vdzd-7h35" } @other{https://resolver.caltech.edu/CaltechTHESIS:04112012-080413185, title = "Type Inference in a Declarationless, Object-Oriented Language", url = "https://resolver.caltech.edu/CaltechTHESIS:04112012-080413185", id = "record", doi = "10.7907/sa4t-bn94" } @other{https://resolver.caltech.edu/CaltechTHESIS:03262012-092805759, title = "A VLSI Combinator Reduction Engine", url = "https://resolver.caltech.edu/CaltechTHESIS:03262012-092805759", id = "record", doi = "10.7907/r471-je71" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-110450092, title = "A Self-Timed Chip Set for Microprocessor Communication", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-110450092", id = "record", doi = "10.7907/tnv1-t713" } @other{https://resolver.caltech.edu/CaltechTHESIS:04112012-082810035, title = "EARL: An Integrated Circuit Design Language", url = "https://resolver.caltech.edu/CaltechTHESIS:04112012-082810035", id = "record", doi = "10.7907/z452-0r86" } @other{https://resolver.caltech.edu/CaltechTHESIS:04132012-091556662, title = "Structure, placement and modelling", url = "https://resolver.caltech.edu/CaltechTHESIS:04132012-091556662", id = "record", doi = "10.7907/tb24-mg70" }